JPS57107638A - Logical cell for integrated circuit - Google Patents

Logical cell for integrated circuit

Info

Publication number
JPS57107638A
JPS57107638A JP55184745A JP18474580A JPS57107638A JP S57107638 A JPS57107638 A JP S57107638A JP 55184745 A JP55184745 A JP 55184745A JP 18474580 A JP18474580 A JP 18474580A JP S57107638 A JPS57107638 A JP S57107638A
Authority
JP
Japan
Prior art keywords
cell
base
input terminal
emitter
terminal
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP55184745A
Other languages
Japanese (ja)
Other versions
JPS6223923B2 (en
Inventor
Kazumasa Nawata
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Fujitsu Ltd
Original Assignee
Fujitsu Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Fujitsu Ltd filed Critical Fujitsu Ltd
Priority to JP55184745A priority Critical patent/JPS57107638A/en
Publication of JPS57107638A publication Critical patent/JPS57107638A/en
Publication of JPS6223923B2 publication Critical patent/JPS6223923B2/ja
Granted legal-status Critical Current

Links

Classifications

    • HELECTRICITY
    • H03ELECTRONIC CIRCUITRY
    • H03KPULSE TECHNIQUE
    • H03K19/00Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
    • H03K19/02Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components
    • H03K19/08Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components using semiconductor devices
    • H03K19/082Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components using semiconductor devices using bipolar transistors
    • H03K19/086Emitter coupled logic

Landscapes

  • Engineering & Computer Science (AREA)
  • Logic Circuits (AREA)
  • Power Engineering (AREA)
  • Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Computing Systems (AREA)
  • General Engineering & Computer Science (AREA)
  • Mathematical Physics (AREA)

Abstract

PURPOSE:To enable to apply the cell to a wider application, by using a transistor (TR) in which the emitter has a resistor and the collector and base have no connection as an output load or input protection. CONSTITUTION:In a cell for OR/NORECL (emitter coupled logic) gate, TRs Q6, Q7, Q8 in which the collector and base have no connection and a resistor is provided between the emitter and the power supply line are provided near the input terminal or output terminal. In the cell, terminals 5 and 6, 7 and 8, 4 and 9, and 4' and 10 are connected, and the base is taken as the input terminal, allowing to obtain an OR/NOR gate having a constant current load. When the terminal 8 is connected to the input terminal 1 and the base of a TRQ8 is kept open, the cell can be used for a protection circuit for the input terminal 1.
JP55184745A 1980-12-25 1980-12-25 Logical cell for integrated circuit Granted JPS57107638A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP55184745A JPS57107638A (en) 1980-12-25 1980-12-25 Logical cell for integrated circuit

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP55184745A JPS57107638A (en) 1980-12-25 1980-12-25 Logical cell for integrated circuit

Publications (2)

Publication Number Publication Date
JPS57107638A true JPS57107638A (en) 1982-07-05
JPS6223923B2 JPS6223923B2 (en) 1987-05-26

Family

ID=16158596

Family Applications (1)

Application Number Title Priority Date Filing Date
JP55184745A Granted JPS57107638A (en) 1980-12-25 1980-12-25 Logical cell for integrated circuit

Country Status (1)

Country Link
JP (1) JPS57107638A (en)

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS59117326A (en) * 1982-12-23 1984-07-06 Toshiba Corp Logical circuit
JPS60144017A (en) * 1983-12-30 1985-07-30 Hitachi Ltd Flip-flop circuit

Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5036952A (en) * 1973-08-08 1975-04-07
JPS5567237A (en) * 1978-11-13 1980-05-21 Hughes Aircraft Co Universal digital array

Patent Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5036952A (en) * 1973-08-08 1975-04-07
JPS5567237A (en) * 1978-11-13 1980-05-21 Hughes Aircraft Co Universal digital array

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS59117326A (en) * 1982-12-23 1984-07-06 Toshiba Corp Logical circuit
JPS60144017A (en) * 1983-12-30 1985-07-30 Hitachi Ltd Flip-flop circuit

Also Published As

Publication number Publication date
JPS6223923B2 (en) 1987-05-26

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