JPS57133725A - Interface circuit - Google Patents

Interface circuit

Info

Publication number
JPS57133725A
JPS57133725A JP56019260A JP1926081A JPS57133725A JP S57133725 A JPS57133725 A JP S57133725A JP 56019260 A JP56019260 A JP 56019260A JP 1926081 A JP1926081 A JP 1926081A JP S57133725 A JPS57133725 A JP S57133725A
Authority
JP
Japan
Prior art keywords
turn
trs
vbe7
vbe5
interface circuit
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP56019260A
Other languages
Japanese (ja)
Inventor
Shinji Sugiyama
Hitoshi Takeda
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Sony Corp
Original Assignee
Sony Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Sony Corp filed Critical Sony Corp
Priority to JP56019260A priority Critical patent/JPS57133725A/en
Publication of JPS57133725A publication Critical patent/JPS57133725A/en
Pending legal-status Critical Current

Links

Classifications

    • HELECTRICITY
    • H03ELECTRONIC CIRCUITRY
    • H03KPULSE TECHNIQUE
    • H03K19/00Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
    • H03K19/01Modifications for accelerating switching
    • H03K19/013Modifications for accelerating switching in bipolar transistor circuits
    • HELECTRICITY
    • H03ELECTRONIC CIRCUITRY
    • H03KPULSE TECHNIQUE
    • H03K19/00Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
    • H03K19/0175Coupling arrangements; Interface arrangements
    • H03K19/018Coupling arrangements; Interface arrangements using bipolar transistors only
    • H03K19/01806Interface arrangements
    • H03K19/01812Interface arrangements with at least one differential stage

Landscapes

  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Physics & Mathematics (AREA)
  • Computing Systems (AREA)
  • General Engineering & Computer Science (AREA)
  • Mathematical Physics (AREA)
  • Analogue/Digital Conversion (AREA)
  • Logic Circuits (AREA)

Abstract

PURPOSE:To achieve stable operation in high speed, by differential connection of the 1st and 2nd transistors (TRs), connecting a diode between the collector of each TR and a reference potential, and applying an output of an ECL circuit to the base of the 1st and 2nd TRs. CONSTITUTION:When signals P1, P1' are applied, TRs Q2, Q5 turn on, and Q1, Q3 turn off. As a result, currents I, I1-I7 flow as shown in figure, where I3 is nearly zero. In this case, the follwing relation is obtained, I=I2+I5+I6, I1R7, I2R2=I6R6, I7R7+VBE7=Vcc-3VF, (I4+I5)R4+VBE5= I2R2 (where; VBE7, VBE5 are respectively base-to-emitter voltage of Q7, Q5). Thus, voltages at output terminals 23, 24 can be 4VF-3VF by suitably selecting the values of R1, R2, R4, allowing to turn on the Q7 and to turn off the Q6.
JP56019260A 1981-02-12 1981-02-12 Interface circuit Pending JPS57133725A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP56019260A JPS57133725A (en) 1981-02-12 1981-02-12 Interface circuit

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP56019260A JPS57133725A (en) 1981-02-12 1981-02-12 Interface circuit

Publications (1)

Publication Number Publication Date
JPS57133725A true JPS57133725A (en) 1982-08-18

Family

ID=11994460

Family Applications (1)

Application Number Title Priority Date Filing Date
JP56019260A Pending JPS57133725A (en) 1981-02-12 1981-02-12 Interface circuit

Country Status (1)

Country Link
JP (1) JPS57133725A (en)

Cited By (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS60124107A (en) * 1983-12-08 1985-07-03 Nec Corp Amplifier circuit
JPS62261225A (en) * 1986-05-07 1987-11-13 Nec Corp Liogic circuit
US4939393A (en) * 1989-10-02 1990-07-03 Motorola Inc. ECL to TTL/CMOS translator using a single power supply
JPH02134739U (en) * 1989-04-13 1990-11-08
JP2011015294A (en) * 2009-07-03 2011-01-20 Nippon Telegr & Teleph Corp <Ntt> Voltage controlled delay generator cell, voltage controlled delay generator and analog/digital converter

Cited By (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS60124107A (en) * 1983-12-08 1985-07-03 Nec Corp Amplifier circuit
JPS62261225A (en) * 1986-05-07 1987-11-13 Nec Corp Liogic circuit
JPH02134739U (en) * 1989-04-13 1990-11-08
US4939393A (en) * 1989-10-02 1990-07-03 Motorola Inc. ECL to TTL/CMOS translator using a single power supply
JP2011015294A (en) * 2009-07-03 2011-01-20 Nippon Telegr & Teleph Corp <Ntt> Voltage controlled delay generator cell, voltage controlled delay generator and analog/digital converter

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