JPS6223923B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a basic cell used in the design of integrated circuit devices, and in particular to a gate cell containing a composite element that can be used as both an output stage load circuit and an input stage protection circuit. It is related to the configuration of.

As the degree of integration of integrated circuit devices (hereinafter abbreviated as IC) has increased, in order to design them more efficiently, it has become possible to use the necessary circuits in cells. This is done by preparing basic cells with standard designs of various circuits such as AND gates and OR gates, placing selected cells in the necessary areas, and selectively wiring within the cell and/or between cells. with the desired functionality by
This is an attempt to form an IC.

One of the basic cells prepared for this purpose is OR/
There is a circuit called a NORECL (emitter coupled logic) gate. This is basically a circuit as shown in Figure 1, and is a type of logic circuit that has the functions of outputting an output signal with the same polarity as the input signal, and outputting it with the opposite polarity. be.

In Figure 1, the load of each output transistor Q ₄ and Q ₅ is a resistor, but in the case of such a resistor termination, the resistance value of R ₁ or R ₂ should be increased to reduce power consumption. is necessary. However, if this resistance is increased, the capacitance of the wiring to the next stage becomes effective and the operating speed decreases, so there is a situation in which the value of this resistance cannot be increased in order to achieve high-speed operation.

To solve this problem, a transistor is used as a load and operated at a constant current. The circuit in that case is as shown in FIG.
Such a circuit achieves high-speed operation and low power consumption, but since the wiring is fixed, there is a problem that power is consumed even when transistors _Q4 or _Q5 are not used.

The present invention solves these problems and also provides a cell structure equipped with a load circuit that can be used as an input protection circuit if necessary, and in which a part of the wiring within the cell can be selected. In a logic cell for an integrated circuit configuration, a circuit consisting of a transistor whose collector and base are not connected, and a resistor connected to the emitter of the transistor and at least one of the power supply lines is connected to the input terminal of the gate circuit. is characterized in that at least one is disposed near the output terminal.

An embodiment of the invention is shown in FIG. In the figure, transistors and resistors are shown using symbols for easy understanding, but in actual ICs, these elements are formed as various impurity diffusion regions formed on a silicon substrate. As in normal cases, the pattern data is prepared as material for automatic design.

In the cell shown in Figure 3, the important point is that the wiring within the cell is left open, as shown in the part marked with □, where no connections are made between elements. The point is that there is. This means that wiring is provided as necessary, and in particular, the circuit shown in Figure 4 is
Unlike the case in Figure 2, it is not connected to the emitters of Q ₄ and Q ₅ , and moreover, it is not connected to the emitters of Q 4 and Q 5, but is connected near the input terminal (base terminal of Q ₁ ) 1 or to the output terminal (the emitter terminal of Q ₄ and Q ₅₎ . )5 and 7 is important.

One of the applications of the circuit shown in FIG. 4 is as a constant current load circuit, as in the prior art. Terminal 5 in Figure 3
Connect 6, 7 and 8, 4 and 9, 4' and 10, 1
If the input terminal is
OR/NOR gate is realized.

Furthermore, the load circuits Q ₈ and R ₃ in the unconnected state
It is also possible to use it as a load for the output of other cells. For example, if you want to take out two OR outputs from the cells shown in Figure 3, as shown in Figure 5, use _Q7 as the load of _Q5 to take out the first output, and connect the output transistor Q equivalent to _Q5 . ₅ ' is newly provided, and the second output is taken out using _Q8 ' of the next stage cell as a load. The previous cell is not this OR/NOR gate,
For example, even in the case of a multi-input OR gate cell whose output is in the form of an open emitter, the load circuit provided in the cell of the present invention can be connected to serve as a load. .

One advantage of leaving the load circuit of the intra-cell output stage unconnected is that the emitter of the output transistor can be left open. Although constant current loads using transistors reduce power consumption, they involve some power consumption. Therefore, it is best to leave the emitter of the output transistor open when there is no need to take out the output to avoid unnecessary power consumption. Therefore, as in the present invention, the output transistor and the load circuit are connected only when necessary. It is advantageous to be connected.

It is also possible to intentionally and easily slow down the operating speed by using a plurality of unconnected load circuits. That is, for example, in Figure 3, if output terminal 7 and load circuits 8 and 2 are connected, and 10 and 4' are connected, and terminal 3 is left open, load circuits Q ₈ and R ₃ are equivalent. It becomes possible to increase the capacity and slow down the operating speed. This is an advantage of arranging the load circuit in an unconnected manner in the present invention.

Furthermore, even if you use an unconnected load circuit and connect the output terminal and the collector terminal of the load circuit, if you leave the base terminal of the load circuit open, unnecessary power consumption can be avoided. This is an advantage of the circuit configuration in which the base terminal of the load circuit can be selectively connected as in the present invention.

Next, a case where the load circuit shown in FIG. 4 is used as an input protection circuit will be explained.

Prevention of electrostatic discharge damage is an important issue in insulated gate ICs, but electrostatic discharge damage can also occur in bipolar ICs. That is, if a high voltage is applied to the input terminal for some reason, a large current will flow even for a short time, which may destroy the PN junction of the input transistor. This occurs regardless of whether the high voltage is in the forward or reverse direction of the junction. Such high voltage applied for a short time can be absorbed by a capacitive circuit.

As shown in Figure 6, input terminal 1 is connected to Q ₈ and
If we connect a circuit consisting of R ₃ and leave the base of Q ₈ open, the transistor can be thought of as two diodes connected in opposite directions, so we can essentially create the circuit shown in Figure 7. It becomes equivalent to the input circuit. Since the diode is a capacitive element, an effect similar to that obtained by connecting a capacitor as shown by the broken line in FIG. 7 can be obtained.

Furthermore, in FIG. 6, the case where the terminal 11 is dropped into one of the power supply lines, that is, the case where _R3 is shorted, is indicated by a broken line, but such usage is also possible.

In this way, the load circuit of the present invention can also be used as a protection circuit.

Considering the usage as described above, the question becomes how many of the above-mentioned load circuits is advantageous to provide in a cell, and it is considered that it is good to provide three for a standard cell. In other words, it is assumed that it will be used for loading the OR and NOR outputs and for input protection, but if it is needed for other purposes, the unnecessary ones can be replaced, so the scope of use of such a cell is limited. It becomes wide. If there is room in the cell, more circuits may be provided; on the other hand, if there is no room, even if only one circuit is provided, the effect is great.

As explained above, the OR/NOR gate cell of the present invention has many uses and is useful for IC design.

[Brief explanation of the drawing]

1 and 2 are diagrams showing the prior art, FIG. 3 is a diagram showing a cell of the present invention, and FIGS. 4 to 7 are diagrams for explaining the present invention. 1-11
are terminals for connection within the cell, Q ₁ to _{Q 8} are transistors,
R ₁ to _{R 3} are resistors, D ₁ , D ₂ are diodes, C ₁ , C ₂ ,
C ₃ is a capacitor, and V _CC and V _EE are power supply lines.

Claims (1)

[Claims] 1. In a logic cell for an integrated circuit configuration in which a part of the wiring within the cell is configured to be selectable, the logic cells have emitters connected in common and collectors connected to a high power supply voltage V through a resistor. first and second transistors Q ₁ and Q ₂ connected to _CC ; output emitter follower transistors Q ₄ and Q ₅ whose bases are connected to the collectors of the first and/or second transistors; The logic cell further includes a current source transistor _Q3 connected between the emitters of the first and second transistors and the low power supply _VEE , and further includes a resistor connected to the low power supply _VEE and an emitter connected to the resistor. A preliminary circuit consisting of a transistor connected to the input terminal of the logic cell connected to the base of the first or second transistor or near the output terminal of the logic cell connected to the emitter of the output emitter follower transistor. A logic cell for an integrated circuit, characterized in that the collector of the transistor of the preliminary circuit is connected to the output terminal or the input terminal, and the base thereof is connected to a predetermined bias potential or to an open circuit, as appropriate.