JPS5672532A - Interface circuit - Google Patents

Interface circuit

Info

Publication number
JPS5672532A
JPS5672532A JP14837879A JP14837879A JPS5672532A JP S5672532 A JPS5672532 A JP S5672532A JP 14837879 A JP14837879 A JP 14837879A JP 14837879 A JP14837879 A JP 14837879A JP S5672532 A JPS5672532 A JP S5672532A
Authority
JP
Japan
Prior art keywords
circuit
turned
mosfet
interface circuit
fet14
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP14837879A
Other languages
Japanese (ja)
Inventor
Hideji Eto
Yoshitaka Kimoto
Katsuaki Utena
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Toshiba Corp
Original Assignee
Toshiba Corp
Tokyo Shibaura Electric Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Toshiba Corp, Tokyo Shibaura Electric Co Ltd filed Critical Toshiba Corp
Priority to JP14837879A priority Critical patent/JPS5672532A/en
Publication of JPS5672532A publication Critical patent/JPS5672532A/en
Pending legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K19/00—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
    • H03K19/0008—Arrangements for reducing power consumption
    • H03K19/0013—Arrangements for reducing power consumption in field effect transistor circuits
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K19/00—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
    • H03K19/0175—Coupling arrangements; Interface arrangements
    • H03K19/0185—Coupling arrangements; Interface arrangements using field effect transistors only
    • H03K19/018507—Interface arrangements
    • H03K19/018521—Interface arrangements of complementary type, e.g. CMOS

Landscapes

  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Physics & Mathematics (AREA)
  • Computing Systems (AREA)
  • General Engineering & Computer Science (AREA)
  • Mathematical Physics (AREA)
  • Manipulation Of Pulses (AREA)
  • Logic Circuits (AREA)

Abstract

PURPOSE:To reduce the electric power consumption by constituting the interface circuit which has been inserted between the bipolar transistor circuit and the MOSFET circuit, by use of MOSFET. CONSTITUTION:The interface circuit 11 is inserted between the bipolar transistor logical circuit 1 and the MOSFET logical circuit 2. And when an output of the circuit 1 is in a low level, the MOSFET12 is turned on, and the terminal OUT3 becomes a high level. When the output of the circuit 1 is in a high level, the MOSFETs 13, 14 are turned on, and the terminal OUT3 becomes a low level. And when the FET14 is turned on, the transistor of the circuit 1 is biased in the reverse direction by the FET14, and therefore the electric power consumption can be reduced.
JP14837879A 1979-11-16 1979-11-16 Interface circuit Pending JPS5672532A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP14837879A JPS5672532A (en) 1979-11-16 1979-11-16 Interface circuit

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP14837879A JPS5672532A (en) 1979-11-16 1979-11-16 Interface circuit

Publications (1)

Publication Number Publication Date
JPS5672532A true JPS5672532A (en) 1981-06-16

Family

ID=15451414

Family Applications (1)

Application Number Title Priority Date Filing Date
JP14837879A Pending JPS5672532A (en) 1979-11-16 1979-11-16 Interface circuit

Country Status (1)

Country Link
JP (1) JPS5672532A (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4703201A (en) * 1984-08-14 1987-10-27 British Telecommunications Plc CMOS Schmitt trigger

Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS49123259A (en) * 1973-03-28 1974-11-26

Patent Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS49123259A (en) * 1973-03-28 1974-11-26

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4703201A (en) * 1984-08-14 1987-10-27 British Telecommunications Plc CMOS Schmitt trigger

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