JPS57201064A - Semiconductor memory cell - Google Patents
Semiconductor memory cellInfo
- Publication number
- JPS57201064A JPS57201064A JP56086209A JP8620981A JPS57201064A JP S57201064 A JPS57201064 A JP S57201064A JP 56086209 A JP56086209 A JP 56086209A JP 8620981 A JP8620981 A JP 8620981A JP S57201064 A JPS57201064 A JP S57201064A
- Authority
- JP
- Japan
- Prior art keywords
- fet
- line
- memory cell
- channel mos
- region
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 239000004065 semiconductor Substances 0.000 title abstract 2
- 230000008878 coupling Effects 0.000 abstract 2
- 238000010168 coupling process Methods 0.000 abstract 2
- 238000005859 coupling reaction Methods 0.000 abstract 2
- 239000000758 substrate Substances 0.000 abstract 2
Classifications
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
- G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
- G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
- G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
- G11C11/401—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming cells needing refreshing or charge regeneration, i.e. dynamic cells
- G11C11/403—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming cells needing refreshing or charge regeneration, i.e. dynamic cells with charge regeneration common to a multiplicity of memory cells, i.e. external refresh
- G11C11/404—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming cells needing refreshing or charge regeneration, i.e. dynamic cells with charge regeneration common to a multiplicity of memory cells, i.e. external refresh with one charge-transfer gate, e.g. MOS transistor, per cell
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
- G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
- G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
- G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
- G11C11/401—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming cells needing refreshing or charge regeneration, i.e. dynamic cells
- G11C11/4063—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing
- G11C11/407—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing for memory cells of the field-effect type
- G11C11/4074—Power supply or voltage generation circuits, e.g. bias voltage generators, substrate voltage generators, back-up power, power control circuits
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
- H01L27/04—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body
- H01L27/08—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind
- H01L27/085—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only
- H01L27/088—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only the components being field-effect transistors with insulated gate
- H01L27/092—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only the components being field-effect transistors with insulated gate complementary MIS field-effect transistors
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10B—ELECTRONIC MEMORY DEVICES
- H10B12/00—Dynamic random access memory [DRAM] devices
Landscapes
- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Computer Hardware Design (AREA)
- Power Engineering (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Semiconductor Memories (AREA)
Abstract
PURPOSE:To increase the output signal of a semiconductor memory cell having first FET, second FET, wiring line, reading line and word line by setting the coupling capacity between the energizing electrode of the second FET and the substrate region of the second FET to the prescribed value. CONSTITUTION:In a memory cell employing MOSTr, P channel MOS is composed of P type first energizing electrode 11, a gate electrode 12, an N type substrate region 13 supplied with a reference voltage, and second energizing electrode 16 of electrically floated state. Similarly, an N channel MOS is composed of the regions 13, 14, 15, 16 and is connected to a reading line RR'. AA' line is a word line. The coupling capacity between the first energizing pole 14 of the N channel MOS and the region 16 is set to less than 80% of the entire capacity of the region 16. In this manner, the reading speed can be accelerated and the output power can be increased.
Priority Applications (2)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP56086209A JPS57201064A (en) | 1981-06-04 | 1981-06-04 | Semiconductor memory cell |
US06/830,919 US4706107A (en) | 1981-06-04 | 1986-02-20 | IC memory cells with reduced alpha particle influence |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP56086209A JPS57201064A (en) | 1981-06-04 | 1981-06-04 | Semiconductor memory cell |
Publications (1)
Publication Number | Publication Date |
---|---|
JPS57201064A true JPS57201064A (en) | 1982-12-09 |
Family
ID=13880383
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP56086209A Pending JPS57201064A (en) | 1981-06-04 | 1981-06-04 | Semiconductor memory cell |
Country Status (1)
Country | Link |
---|---|
JP (1) | JPS57201064A (en) |
Cited By (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS6278799A (en) * | 1985-07-19 | 1987-04-11 | テキサス インスツルメンツ インコ−ポレイテツド | Dynamic random access memory cell |
Citations (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS5357777A (en) * | 1976-11-04 | 1978-05-25 | Hitachi Ltd | Semiconductor memory device |
-
1981
- 1981-06-04 JP JP56086209A patent/JPS57201064A/en active Pending
Patent Citations (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS5357777A (en) * | 1976-11-04 | 1978-05-25 | Hitachi Ltd | Semiconductor memory device |
Cited By (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS6278799A (en) * | 1985-07-19 | 1987-04-11 | テキサス インスツルメンツ インコ−ポレイテツド | Dynamic random access memory cell |
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