JPS5721856A - Semiconductor memory cell - Google Patents

Semiconductor memory cell

Info

Publication number
JPS5721856A
JPS5721856A JP9670280A JP9670280A JPS5721856A JP S5721856 A JPS5721856 A JP S5721856A JP 9670280 A JP9670280 A JP 9670280A JP 9670280 A JP9670280 A JP 9670280A JP S5721856 A JPS5721856 A JP S5721856A
Authority
JP
Japan
Prior art keywords
electrode
type
memory cell
energization
reference potential
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP9670280A
Other languages
Japanese (ja)
Inventor
Kazuo Terada
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
NEC Corp
Original Assignee
NEC Corp
Nippon Electric Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by NEC Corp, Nippon Electric Co Ltd filed Critical NEC Corp
Priority to JP9670280A priority Critical patent/JPS5721856A/en
Publication of JPS5721856A publication Critical patent/JPS5721856A/en
Pending legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B12/00—Dynamic random access memory [DRAM] devices

Landscapes

  • Bipolar Transistors (AREA)
  • Semiconductor Memories (AREA)

Abstract

PURPOSE:To facilitate microminiaturization of a semiconductor memory cell by forming respectively an address line and a digit line. CONSTITUTION:This memory cell is composed of the first MOSFET of P-channel having a gate electrode 101, a P type first energization electrode 102, a P type second energization electrode 103 of electrically floated state and an N type substrate region 104 supplied with reference potential, and the second MOSFET of N channel composed of a gate electrode 105, an N type first energization electrode 106, an N type second energization electrode 107 supplied with reference potential, and a P type substrate region 108 of electrically floated state and connected directly to the electrode 103, the digit line 110 is connected directly to the electrode 102, and is connected via a resistor 109 to the electrode 106, and the address line 111 is commonly connected to the respective gate electrodes 101, 105. Further, a power source terminal 112 for providing reference potential is provided.
JP9670280A 1980-07-15 1980-07-15 Semiconductor memory cell Pending JPS5721856A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP9670280A JPS5721856A (en) 1980-07-15 1980-07-15 Semiconductor memory cell

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP9670280A JPS5721856A (en) 1980-07-15 1980-07-15 Semiconductor memory cell

Publications (1)

Publication Number Publication Date
JPS5721856A true JPS5721856A (en) 1982-02-04

Family

ID=14172086

Family Applications (1)

Application Number Title Priority Date Filing Date
JP9670280A Pending JPS5721856A (en) 1980-07-15 1980-07-15 Semiconductor memory cell

Country Status (1)

Country Link
JP (1) JPS5721856A (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6875651B2 (en) * 2003-01-23 2005-04-05 Sharp Laboratories Of America, Inc. Dual-trench isolated crosspoint memory array and method for fabricating same

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6875651B2 (en) * 2003-01-23 2005-04-05 Sharp Laboratories Of America, Inc. Dual-trench isolated crosspoint memory array and method for fabricating same
CN1303665C (en) * 2003-01-23 2007-03-07 夏普株式会社 Dual-trench isolated crosspoint memory array and method for fabricating same

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