JPS5712483A - Transistor circuit - Google Patents

Transistor circuit

Info

Publication number
JPS5712483A
JPS5712483A JP8473580A JP8473580A JPS5712483A JP S5712483 A JPS5712483 A JP S5712483A JP 8473580 A JP8473580 A JP 8473580A JP 8473580 A JP8473580 A JP 8473580A JP S5712483 A JPS5712483 A JP S5712483A
Authority
JP
Japan
Prior art keywords
signal
potential
precharge
power supply
phip1
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP8473580A
Other languages
Japanese (ja)
Other versions
JPS618515B2 (en
Inventor
Toshio Wada
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
NEC Corp
Original Assignee
NEC Corp
Nippon Electric Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by NEC Corp, Nippon Electric Co Ltd filed Critical NEC Corp
Priority to JP8473580A priority Critical patent/JPS5712483A/en
Publication of JPS5712483A publication Critical patent/JPS5712483A/en
Publication of JPS618515B2 publication Critical patent/JPS618515B2/ja
Granted legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
    • G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
    • G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
    • G11C11/401—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming cells needing refreshing or charge regeneration, i.e. dynamic cells
    • G11C11/4063—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing
    • G11C11/407—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing for memory cells of the field-effect type
    • G11C11/409—Read-write [R-W] circuits 
    • G11C11/4094—Bit-line management or control circuits

Landscapes

  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Computer Hardware Design (AREA)

Abstract

PURPOSE:To obtain a precharge circuit of a large-scale MOS memory having a small power consumption plus a high stability and high reproducibility, by making the precharge circuit for signal line induce the bootstrap to the precharge signal. CONSTITUTION:The potentials of a pair of signal lines D and D' are first set at a high and low level respectively, and the balancing proceeds due to the face that MISFETQ1, Q2 and Q10 conduct with an increase of potential of the precharge signal phip1. With an increase of precharge signal phip2, MISFETQ3 and Q4 in a depression state conduct remarkably, and the output side of the FET rises up to the potential of the power source VDD. In this case, FETQ1, Q2 and Q10 produce the bootstrap effect to the gate electrode since the drain side increases up to the power supply potential. As a result, the potential of signal phip1 is raised up to the level higher than the power supply voltage. Thus lines D and D' reach the power supply potential. Then the signal difference is amplified when the word signal phiw is driven.
JP8473580A 1980-06-23 1980-06-23 Transistor circuit Granted JPS5712483A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP8473580A JPS5712483A (en) 1980-06-23 1980-06-23 Transistor circuit

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP8473580A JPS5712483A (en) 1980-06-23 1980-06-23 Transistor circuit

Publications (2)

Publication Number Publication Date
JPS5712483A true JPS5712483A (en) 1982-01-22
JPS618515B2 JPS618515B2 (en) 1986-03-14

Family

ID=13838946

Family Applications (1)

Application Number Title Priority Date Filing Date
JP8473580A Granted JPS5712483A (en) 1980-06-23 1980-06-23 Transistor circuit

Country Status (1)

Country Link
JP (1) JPS5712483A (en)

Cited By (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP0154547A2 (en) * 1984-03-09 1985-09-11 Kabushiki Kaisha Toshiba A dynamic read-write random access memory
JPS62145597A (en) * 1985-12-19 1987-06-29 Mitsubishi Electric Corp Semiconductor memory device
JPS62223889A (en) * 1986-03-26 1987-10-01 Toshiba Corp Booster circuit in semiconductor integrated circuit
JPS62223886A (en) * 1986-03-26 1987-10-01 Toshiba Corp Semiconductor memory
FR2667193A1 (en) * 1990-09-25 1992-03-27 Sgs Thomson Microelectronics PRELOADING CIRCUIT FOR MEMORY READING.
JP2003092364A (en) * 2001-05-21 2003-03-28 Mitsubishi Electric Corp Semiconductor memory device

Families Citing this family (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS6173514U (en) * 1984-07-10 1986-05-19

Cited By (8)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP0154547A2 (en) * 1984-03-09 1985-09-11 Kabushiki Kaisha Toshiba A dynamic read-write random access memory
US4794571A (en) * 1984-03-09 1988-12-27 Kabushiki Kaisha Toshiba Dynamic read-write random access memory
JPS62145597A (en) * 1985-12-19 1987-06-29 Mitsubishi Electric Corp Semiconductor memory device
JPS62223889A (en) * 1986-03-26 1987-10-01 Toshiba Corp Booster circuit in semiconductor integrated circuit
JPS62223886A (en) * 1986-03-26 1987-10-01 Toshiba Corp Semiconductor memory
FR2667193A1 (en) * 1990-09-25 1992-03-27 Sgs Thomson Microelectronics PRELOADING CIRCUIT FOR MEMORY READING.
US5258955A (en) * 1990-09-25 1993-11-02 Sgs-Thomson Microelectronics, S.A. Pre-charging method for the reading of memories
JP2003092364A (en) * 2001-05-21 2003-03-28 Mitsubishi Electric Corp Semiconductor memory device

Also Published As

Publication number Publication date
JPS618515B2 (en) 1986-03-14

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