JPS62145597A - Semiconductor memory device - Google Patents

Abstract

PURPOSE:To suppress a peak current as a whole in the pre-charge operation time of a bit line in a semiconductor storage device of large capacity, and to stable an equalize operation by constituting a device so as to set the equalize and the node of a pre-charge part separately. CONSTITUTION:When a clock signal phi1 becomes a high level, a MOS transistor Q1 is turned on, and the bit lines BL and the inverse of BL are equalized at intermediate levels of potentials respectively. Next, a clock signal phi2 becomes the high level, and transistors Q2 and Q3 are turned on, and a current flows from a pre-charge voltage V1 to the bit lines BL and the inverse of BL, and the bit lines BL and the inverse of BL are pre-charged to the pre-charge voltage V1 respectively. The peak voltage at that time is not overlapped with the equalize operation, and it can be suppressed at a small peak current comparatively, and the reduction in the peak voltage can be attained judging from the whole of the device.

Description

[Detailed description of the invention] [Industrial application field] The present invention relates to a semiconductor memory device.

[Conventional technology]

An example of a conventional semiconductor memory device is shown in FIG. 3 and will be described.

In the figure, MC1 to MCn are memory cells arranged in a matrix, and W1 to Wn are memory cells MCl -
Row selection signal to select data of 1xlc n, BL, B
L denotes a bit line 8 and a bit line, respectively, and the bit line BL is configured such that data of a memory cell selected by row selection signals W1 to Vn is transmitted. The dummy cell DC is connected. SA is a sense amplifier circuit section (sense up) that senses the level difference between the two bit lines BL and L)L.

)°C is a precharge section, and MOS transistor Q4. It is composed of QS and Q6. In addition, V2
indicates the precharge level potential (Vcc), and φ5.
φ4 indicates a clock signal.

The operation of the semiconductor memory device constructed in this way will be explained with reference to FIG. 4.

This FIG. 4 is a time chart used to explain the operation of FIG. 3, and shows the precharge section PC's precharge timing, charge timing, and current waveform.

(a) shows the potentials of the bit lines BL, BL, (b) shows the clock signal φg, and (C) shows the clock signal φt, (d'l?u power supply tolerance ■cc and the bit line L
It shows the current between iL or bit line Bl.

Here, the precharge level potential v3 is considered to be the power supply voltage VCC for explanation.

First, before time t, the bit lines BL and BL are at a high level or a low level due to the operation of the sense amplifier SA, corresponding to the levels of the memory cells MC1 to MC1 to Men and the dummy cell DC. a)). Here, the sense amplifier 8A is inactive and enters the precharge operation of the pit 1BL (bit 11BL).

Then, the clock signal φ3 is 1 Terama 1. -16, the level changes from low level to high level as shown in the waveform (in Figure 4).
MOS transistor Q41Q5 turns on and bit line BL
, pit line BL is equalized and at the same time, since clock signal φ·t is at the level of power supply voltage Vcc, V
I can't even precharge the cc-VTR. Here, the power supply voltage Vcc and the sibbit line BL.

Next, at time t, ~t, the clock signal φ4 is activated as shown in FIG.
As shown in the waveform of C'l, from the power supply voltage Vcc level to V
Bit line BL must be at a level higher than cc + VTH.

The bit line BL is at a precharge level of 1) VIK.

[Problem that the invention seeks to solve]

In the conventional semiconductor memory device described above, the precharge section is configured as described above, so that the precharge operation is performed to some extent simultaneously during the bit line equalization operation.
At this time, there is a problem in that a large current flows between the power supply voltage Vcc and the bit line.

In recent large-capacity semiconductor memory devices, the bit line capacitance also increases as the capacity increases, and especially when the bit line is made of a low impedance material such as A7, the peak current during precharge operation is large. 1. If the timing overlaps with other circuit operations, fluctuations in the power supply voltage Vcc and ground voltage become temporarily large, which poses a problem in terms of device implementation.

The present invention has been made to solve these problems, and provides a semiconductor memory device that can suppress the increase in peak current as a whole during precharge operation and stabilize equalization operation. The purpose is to

[Means for solving problems]

In the semiconductor memory device according to the present invention, memory cells are arranged in a matrix, data of a memory cell selected by a row selection signal is transmitted to a first bit line, and a dummy cell is connected to the other second pit line. A sense amplifier that senses the level difference between these two bit lines is connected to the first and second bit lines, and the sense amplifier senses and amplifies the voltage difference between the first and second bit lines. The circuit is designed to include a precharge section that equalizes both bit lines and precharges them to a predetermined level before processing.

[Effect]

In the present invention, in the precharge section of the semiconductor memory device, the part that equalizes the bit lines and the part that connects to the precharge potential and precharges are separated, and the equalization operation becomes more stable. , since the precharge-only operation does not overlap with other equalization operations, etc.
Overall, the peak current value becomes smaller.

〔Example〕

Embodiments of the present invention will be described in detail below based on the drawings.

FIG. 1 is a block diagram showing an embodiment of a semiconductor memory device according to the present invention, and only the parts necessary for explanation are shown.

In FIG. 1, the same reference numerals as in FIG. 3 indicate corresponding parts. This precharge section P equalizes and precharges to a certain predetermined level.
C has a drain connected to the bit line BL and a source connected to the bit line B.
an MO8 transistor Q1 whose drain is connected to the bit line BL, whose source is supplied with a precharge voltage v1, and whose gate is supplied with a clock signal φ2. and an MO8 transistor Q whose drain is connected to the bit line BL, whose source is supplied with the precharge revoltage v1, and whose gate is supplied with the clock signal φ2.
It is composed of 8.

Next, the operation of the embodiment shown in FIG. 1 will be explained with reference to FIG. 2.

Figure 2 is a time chart used to explain the operation of Figure 1.
5 shows the timing and current waveform during a precharge operation of the precharge unit PC. (a) shows the bit line BL and the potential of the bit line BL, (■) shows the clock coefficient φ1, and (C) shows the clock signal φ
2, (d) shows the current between the power supply voltage Vcc and the bit line BL or the bit line BL.

First, before time t, the bit line BL and pit line BL are at a high level or a low level due to the operation of the sense amplifier 8A (see FIG. 2(a)). And time '1
At tt, the clock signal φ1 becomes high level as shown in the waveform of FIG. 2('b), and the j7, MO, S transistor Q
1 is turned on, and the bit lines BL and BL are equalized to near the intermediate potential of their respective potentials.

At the time t3-t4, the clock signal φ becomes as shown in FIG.
As shown in the waveform of C), when the level is high, MOS transistors Q, Q8 are turned on, and current flows from the precharge voltage Vl to the bit line BL. Each precharge voltage
will be precharged.

The peak current at this time is 1. -1. the time in between and
Although it depends on other operating currents at this time, it does not overlap with the equalizing operation, and by changing the time t, the peak current can be suppressed to a relatively small value.

In this way, the precharge unit PC uses the clock signal φ during the precharge operation.

There is no high level before the bit line BL and the same line BL.
By setting the clock signal φ to the same level and then increasing the clock signal φ to a high level over a certain period of time since the operating time is different from that of other circuits, it is possible to reduce the peak current when looking at the device as a whole.

In addition, in the above embodiment, the precharge voltage is set to the power supply voltage V
cc, but other levels, e.g.
It may be at a level higher than the source voltage Vcc, and the same effects as in the above embodiment can be achieved.

〔Effect of the invention〕

As explained above, according to the present invention, since the equalization node of the precharge section and the node of the precharge section are configured to be different from each other, the overall Since the peak current can be suppressed and the equalization operation can be stabilized, the practical effects are outstanding.

[Brief explanation of drawings]

FIG. 1 is a block diagram showing an embodiment of a semiconductor memory device according to the present invention, FIG. 2 is a time chart for explaining the operation of FIG. 1, and FIG. 3 is an example of a conventional 5 semiconductor memory device. The configuration diagram and FIG. 4 are time charts for explaining the operation of FIG. 2]13. SA...-Sense amplifier, MC1 to MCn...Memory cell, BL, BL...Bit i, DC/e...
Dummy cell, PC...precharge section, Q l-Q
, s III IN10S transistor.

Claims (3)

[Claims] (1) Memory cells are arranged in a matrix, data of a memory cell selected by a row selection signal is transmitted to a first bit line, a dummy cell is connected to the other second bit line, and a dummy cell is connected to the first and second bit lines. A sense amplifier that senses the level difference between the two bit lines is connected to the second bit line, and before the sense amplifier senses and amplifies the voltage difference between the first and second bit lines, 1. A semiconductor memory device comprising a precharge section that equalizes both bit lines and precharges them to a predetermined level. (2) The precharge section has a drain connected to the first bit line,
The source is connected to the second bit line, and the gate is connected to the first bit line.
a first MOS transistor to which a clock signal is supplied; a second MOS transistor whose drain is connected to the first bit line, whose source is supplied with a precharge voltage and whose gate is supplied with a second clock signal; Second
a third clock connected to the bit line, having a source supplied with the precharge voltage and a gate supplied with the second clock signal;
2. A semiconductor memory device according to claim 1, comprising a MOS transistor. (3) In the precharge section, during the precharge operation, the first clock signal becomes high level before the second clock signal,
The first bit line and the second bit line are set to the same level, and then the second clock signal has a different operation time than other circuits, and the second clock signal takes a required time to reach a high level, so that when viewed from the perspective of the entire device. The semiconductor memory device according to claim 1 or 2, characterized in that the peak current of the semiconductor memory device can be reduced.