JPS6020388A - Semiconductor memory - Google Patents

Abstract

PURPOSE:To suppress the capacity unbalance between bit lines and prevent deterioration in sensitivity by adding reference capacity which is almost as large as cell capacity selectively to a bit line opposite to a bit line to which memory cell information is read out. CONSTITUTION:A bit line balance circuit BB includes transistors (TR)T1 and T2 which are connected at drains to a couple of bit lines B0 and B1 and connected in common at sources, the 1st and the 2nd dummy word lines PB0 and PB1 which are connected to the gates of the TRs, and the reference capacitor CR which has the 1st electrode connected to the source of the T1 and the 2nd elecctrode held at a constant potential and also has almost the same capacity that memory cells MC0 and MC1 have. Thus, the reference capacitor is added selectively to a bit line opposite to a bit line to which memory cell information is read out to suppress the capacity unbalance between the bit lines and prevent the deterioration in sense amplifier sensitivity.

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a semiconductor memory, and more particularly to a semiconductor memory in which a bit re-precharge level is directly used as a reference level when a sense amplifier is activated. In addition, for convenience, all of the following are N-channel MO8F
An example using ET will be explained, but the present invention
An example of a conventional semiconductor memory is shown in FIG. 1, and its operating waveforms are shown in FIG. 2. Shown below. In FIG. 1, SA is a sense amplifier, MCO, MCI hahi) 61 A dynamic memory cell, upO, which is connected to BO and Bl, respectively, and stores binary information as a charge value in a cell capacitor C8.
*upl is a pull-up circuit, WO, Wl are word lines, V
R is a reference power supply.

The operation shown in FIG. 1 will be explained according to FIG. First, the bit line capacitance CB for the precharge signal P and the level signal
is set at the node 1'Ju and the reference power supply VR. After turning off these signals P p P u, the bit line balance signal PB is also turned off, and the bit line BO.

Separate Bl. However, although the signal sum is equal to VR, it is maintained at a level slightly lower than VR. Next, by setting the word line ■ to a high level, the memory cell kMc is activated.

The information stored in the cell capacitor C8 is read out onto the bit line as a minute signal. At this time, bit a
I30 becomes a read level determined by the amount of charge stored in the dynamic memory cell MCO and CB/C8.

The solid lines and broken lines of BO and Bl in FIG. 2 indicate the operation waveforms when reading %OJF and %11 information of the memory cell, respectively.

Next, the sense enable signal SE is slowly brought to a low level to activate the sense amplifier SA, and the lower level bit lines BO and B1 are pulled down to the GND level, and then the pull-up enable signal PK is brought to a high level. By raising the higher level of the bit line pair to the VD level, the minute signal read onto the bit line is amplified.

In such a conventional semiconductor memory, the total capacitance attached to the bit lines BO and Bl during amplification of a small signal is CB+C8CB,
There was a problem in that the sensitivity of the 9-sense amplifier was degraded due to imbalance due to the cell capacitance C8.

An object of the present invention is to provide a semiconductor memory that does not cause deterioration in sense amplifier sensitivity even when a bit line precharge level is used as it is as a reference level when the sense amplifier is activated.

That is, the present invention includes at least one sense amplifier;
A pair of bit lines connected to the sense amplifier and having electrically equal characteristics, a plurality of dynamic memory cells connected to the bit line and storing binary information as an amount of charge in a cell capacitor, and a convex memory cell. In a semiconductor memory that is equipped with a word line for easy access and a bit line balance circuit, the precharge level of the bit line is used as a reference level when the sense amplifier is activated.
The bit line balance circuit includes first and second transistors whose respective drains are connected to the pair of bit lines and whose sources are commonly connected, and each of the first and second transistors. Q”r connected to the gate
The first electrode is commonly connected to the first and second dummy word lines and the source of the picture transistor, and the second electrode is kept at a constant potential. This semiconductor memory is characterized in that it is configured with a reference capacitor having .

The present invention will be explained in detail below using a typical embodiment to aid understanding. Figure 3 is a circuit diagram around a sense amplifier showing one embodiment of the present invention, and shows the same part as Figure 1. 1 uses the same symbol. This operation waveform is shown in Figure 4.

In FIG. 3, BB is a bit line balance circuit according to the present invention. This circuit has the following configuration.

That is, the pair of bit lines BO.

first and second transistors Ti whose respective drains are connected to B1 and whose sources are commonly connected;
-Tt, and first and second dummy word lines PBO, FBI connected to the respective gates of both transistors TI, T;
and a reference capacitor CR having a capacitance value comparable to that of the dynamic memory cells MCO and MCI, the first electrode of which is connected to the source of the first transistor T8, and the second electrode of which is kept at a constant potential. It is composed of. PBO and PBl are dummy word lines and are set to be at a high level in a standby state and to be at a low level in a select state.

The operation of Fig. 3 will be explained according to Fig. 4. First,
The precharge signal P sets the reference capacitance CR and bit line capacitance CB to the reference level V through the node NR.
After turning off this signal P, if you want to read information from the memory cell MCO, set the dummy word line PBO to a low level, isolate the bit lines BO and Bl, and set the reference capacitor CR to the bit line. Attach it to the line Bl side. Now set the word rest WO to a high level and the memory cell 8r
A minute signal is read out from O onto the bit line support.

Next, the sense enable signal SE is set to a low level to activate the sense amplifier SA, and the pull-up circuit is activated to amplify the minute signal read onto the bit line pair, as in the conventional case. At this time, the total capacitance attached to the bit lines BO and Bl is CB+C8, CB+CR;'c Ah! 0C
If 3-CR is used, there will be almost no variation in capacitance between bit lines, and the sensitivity of the sense amplifier will not deteriorate.

As detailed above, in the semiconductor memory of the present invention, by selectively adding a reference capacitance of approximately the same size as the cell capacitance to the bit line opposite to the bit line from which memory cell information is read, Capacitance imbalance between bit lines can be suppressed and deterioration of sense amplifier sensitivity can be prevented.

Furthermore, the present invention has the advantage that it can be applied to a folded bit line system in which a pair of bit lines for one sense amplifier are arranged side by side, making it possible to easily arrange the circuit.

[Brief explanation of the drawing]

Figure 1 is a circuit diagram showing an example of a conventional semiconductor memory, Figure 2 is a circuit diagram showing an example of a conventional semiconductor memory.
1, FIG. 3 is a circuit diagram showing an embodiment of the semiconductor memory of the present invention, and FIG. 4 is an operation waveform diagram of FIG. 1. In the figure, SA is a sense amplifier, MCO and MCI are memory cells, BB is a bit line balance circuit, and BO. B1 is a bit line, wo and wi are word lines, PBO, F
BI is a dummy word line, CR is a reference capacitor, P is a precharge signal line, T1. T represents a transistor, respectively. Patent applicant NEC Corporation Figure 1 m'q- B'I, N-shaku , --, /

Claims (1)

[Claims] (1) At least one sense amplifier, a pair of bit lines connected to the sense amplifier and having electrically equal characteristics, and connected to the bit line and storing binary information as an amount of charge in a cell capacitor. In a semiconductor memory comprising a plurality of dynamic memory cells, a word line for accessing the memory cells, and a bit line balance circuit, the bit line precharge level is used as a reference level when the sense amplifier is activated. A first line balance circuit having a drain connected to the pair of bit lines and a common source connected to each other.
and a second transistor, first and second dummy word lines connected to respective gates of the first and second transistors, a first electrode commonly connected to the sources of both transistors, and a first electrode connected to the sources of both transistors in common. 1. A semiconductor memory comprising a reference capacitor having a capacitance comparable to the cell capacitance of the dynamic memory cell whose second electrode is kept at a constant potential.