JPS6333240B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a semiconductor memory device, and more particularly to a dynamic memory device having a memory cell constituted by one transistor and one capacitor.

With the remarkable progress in integrated circuit technology in recent years, large-scale, large-capacity LSIs (Large-Scale Integrated Circuits) have been developed, and in the field of dynamic RAM (random access memory), 64k bits are being mass produced, and 256k bits are being developed. is in progress.

Dynamic RAM has been developed to have a larger capacity due to miniaturization of its constituent elements, and as a result, the power supply voltage has been lowered, and the majority of 4k and 16k bit RAMs are +
While it operated on a high power supply of 12V, ±5V, some 16k-bit RAM and 64k-bit RAM were improved to operate on a single low power supply of +5V. With such a single power supply, the semiconductor substrate voltage (-5V for 4k and 16k bit RAM) has traditionally been applied from outside the chip.
However, by providing a substrate voltage generator on the chip, such an external voltage supply is no longer necessary. This substrate voltage is effective in reducing the pn junction capacitance, reducing various leakage currents, and controlling the threshold voltage of the transistor.

By the way, it is difficult to provide the substrate voltage generator provided on this chip with a sufficiently low impedance as a power source due to its structure. Therefore, it is susceptible to various noises. One example is
For 64k bit RAM, typically 256 or 512
When a real bit line charges and discharges at the same time, the substrate voltage fluctuates greatly due to capacitance coupling between the bit line and the substrate. In a 64k bit RAM, the amplitude of this substrate potential fluctuation is generally about 1V for a 5V bit line charge/discharge amplitude. This fluctuation in substrate potential has an adverse effect on the operation of the chip, especially the circuits that are generally in a high impedance state.

In order to suppress the width of such fluctuations, the capacitive coupling capacitance between the bit line and the substrate can be reduced by replacing the bit line wiring, which was conventionally constructed with an impurity diffusion layer, with aluminum or polycrystalline silicon. Improvements have been made such as reducing the amount of noise, or placing a smoothing capacitor between the substrate and ground potential.

Here, FIG. 1 shows a conventional dynamic RAM in which a plurality of memory cells 1 and two groups of sense amplifiers arranged in a matrix are divided into first and second blocks 3 and 4, for example. Such block division is performed for the purpose of improving the S/N ratio, operating speed, or reducing the number of refresh circuits, and the sense amplifier activation clock _φSE is wired in common.
All sense amplifiers 2 in both blocks 3 and 4 operate to charge and discharge the bit line BL. That is, when the memory cell 1 connected to the word line WL1 of the first block 3 is accessed, the word line WL2 of the second block 4, which has an equivalent relationship with this word line WL1, is also activated, and this word line All memory cells 1 connected to WL2 are refreshed. In addition, this dynamic
In the RAM, memory cells 1 and sense amplifiers 2 are operated by a precharge clock φ _P , a sense amplifier energizing clock φ _SE , a word line WL signal for memory selection, etc. with timings as shown in FIG.
Therefore, as described above, in this memory, the potential of the substrate fluctuates due to charging and discharging of the bit line BL.

In addition, dynamic RAM as shown in Figure 3
is being considered. This memory is also divided into two blocks as in Fig. 1, but sense amplifier energizing clocks are provided independently as _φSE1 and _φSE2 corresponding to each block, so that either one of them can be activated during one memory cycle. It is now energized. For example, the word line in the first block 3
Any one memory cell 1 connected to WL1
Consider when is accessed. At this time, the word line
WL1 is activated, then sense amplifier activation clock _φSE1 is activated, and reading or writing of memory cell 1 is performed. On the other hand, the word line
Word line in second block 4 corresponding to WL1
WL2 and clock φ _SE2 are not energized as shown by the dotted line in the time chart of FIG.
The circuit in block 4 does not operate, and the bit line BL is in a floating state.

In the memory shown in Figure 3 above, the main purpose is to reduce power consumption and instantaneous power consumption, and the number of bit lines BL that are charged and discharged within one memory cycle is halved compared to that in Figure 1. As a result, power consumption is significantly reduced. Further, fluctuations in substrate potential are also reduced to about 1/2. However, as shown in Figure 3, during precharging (precharge cycle)
Since the precharge clock _φP , which precharges the bit line BL and the sense amplifier 2, is wired in common with the first and second blocks 3 and 4, when it is active, all the bit lines of the second block 4 are connected. It will be left in a high impedance floating state. For this reason, conventional dynamic RAM still suffers from fluctuations in substrate potential, which poses some drawbacks in terms of reliability.

The present invention was made in view of the above circumstances, and
The memory cells and sense amplifiers are divided into blocks and arranged, and the precharge circuit that charges the bit lines and sense amplifiers in blocks that do not include memory cells that are accessed in one memory cycle is cut off even when the RAM is active. The capacitance between the bit line charged by this and the board functions as a smoothing capacitor, thereby reducing power consumption without increasing power consumption.
It is an object of the present invention to provide a reliable dynamic memory device that can suppress fluctuations in substrate voltage to a small level with a simple circuit.

Hereinafter, one embodiment of the present invention will be described with reference to the drawings. The dynamic RAM shown in FIG. 5 is also composed of one transistor Q and one capacitor C as described above, and a plurality of memory cells 1 and two groups of sense amplifiers are arranged in a matrix. It is divided into two blocks 3 and 4.
Further, a word line WL for selecting a memory cell and a bit line BL for reading and writing data are commonly connected to these memory cells 1. Further, the sense amplifier 2 in the first block 3 is supplied with a first sense amplifier energizing clock φ _SE1 and a first precharge clock φ _P1 for precharging the sense amplifier 2. A second sense amplifier energizing clock _φSE2 and a second precharge clock _φP2 for precharging the sense amplifier 2 are supplied to the sense amplifier 2 in the sense amplifier 4.

Now, in the first block 3, if one of the memory cells 1 connected to the word line WL1 is accessed after being precharged by the precharge clock _φP1 as shown in FIG. The amplifier energizing clock φ _SE1 is energized as shown by the solid line in FIG. 6, and at this time, the word line WL2 in the second block 4 and the second sense amplifier energizing clock φ _SE2 are activated as shown by the dotted line in FIG. is not biased. In addition, in this case, the first precharge clock φ _P1 of the first block 3 including the memory cell 1 to be accessed is lowered to the ground potential when it is active, as shown by the solid line in FIG. The second block 4 does not contain any memory cells.
Even when the precharge clock _φP2 is active, it is kept at a high potential as shown by the dotted line in FIG. Here, the high potential of the precharge clocks φ _P1 and φ _P2 increases the potential between the bit lines BL arranged in a pair with the sense amplifier 2 in between at high speed and almost equally during the precharge cycle. Power supply to precharge to potential
The voltage value shall be set to _Vcc or higher. Therefore,
All the bit lines BL in the second block 4 are connected to the transistors Q ₂₁ , Q ₂₂ , Q ₂₃ , Q ₂₄ of the sense amplifier 2.
When active, it is also connected to the power supply V _cc via etc.
As a result, all the bit lines BL in the second block 4 function as smoothing capacitors between the board and the power supply _Vcc , and the bit lines BL in the first block 3
Fluctuations (fluctuations) in substrate potential caused by charging and discharging BL
It acts to suppress the

Therefore, according to the embodiment described above, fluctuations in substrate potential can be suppressed to a smaller level than in conventional memories. Furthermore, the word line WL shown in Fig. 3 is added to the circuit that generates the conventional precharge clock _φP .
By selecting one of 1 and WL2 and combining one of the energizing address signals, a selection circuit for two types of precharge clocks φ _P1 and φ _P2 can be easily realized, and the circuit can be particularly complicated. , without increasing power consumption.

In the above embodiment, the memory cell 1 and the sense amplifier 2 group are divided into two blocks, but they may be divided into a plurality of other blocks. In this case, as described above, a circuit for generating a precharge clock corresponding to the block may be provided.

As explained above, according to the present invention, memory cells and sense amplifier groups are divided into blocks and arranged, and a precharge circuit charges bit lines and sense amplifiers in blocks that do not include memory cells accessed in one memory cycle. of
The RAM operates without interruption even when it is active, and the capacitance between the charged bit line and the board functions as a smoothing capacitor, making it possible to simplify the circuit without increasing power consumption. Therefore, fluctuations in substrate potential can be suppressed to a small level, and a reliable dynamic memory device can be provided.

[Brief explanation of the drawing]

Figures 1 to 4 show conventional dynamic RAM
FIG. 5 is a block diagram of a main part of a dynamic RAM according to an embodiment of the present invention, and FIG. 6 is a time chart for explaining the operation of the dynamic RAM shown in FIG. 1...Memory cell, 2...Sense amplifier, 3...
...1st block, 4...2nd block, WL...
Word line, BL...Bit line, _Vcc ...Power supply, _φP1 ,
_φP2 ...Precharge clock, _φSE1 , _φSE2 ...Sense amplifier activation clock, _Q11 to _Q14 , _Q21 to _Q24
...Transistor.

Claims (1)

[Scope of Claims] 1. A dynamic memory device in which a plurality of memory cells each consisting of one transistor and one capacitor are arranged in a matrix on a semiconductor substrate, comprising: the plurality of memory cells and the memory cell; The multiple word lines, bit lines, and sense amplifiers connected to the memory are divided into multiple blocks, and when the storage device is active, the sense amplifiers and bit lines in the blocks that do not include memory cells that are accessed during one memory cycle are divided into multiple blocks. A dynamic storage device characterized in that the precharge clock for precharging the bit line and sense amplifier in the block is kept at a high voltage higher than the power supply voltage during precharging without being energized.