JPH0159680B2 - - Google Patents

Description

[Detailed description of the invention] The present invention relates to semiconductor memories.

Generally, during a read operation of the dynamic MOS memory cell _M00 connected to the digital sense line _D0 as shown in the upper part of FIG.
When a predetermined voltage is applied to the read selection line _R0 , the transistor _Q1 is turned on, and a voltage corresponding to the level of the gate voltage of the transistor _Q2 appears on the digit sense line _D0 , and the level of this voltage is transmitted to the surrounding area. Detected by sense circuit. However, as semiconductor memories become more highly integrated, the area occupied by memory cells becomes smaller, and the load capacity of selected memory cells becomes smaller.
C ₀ tends to be large, so speeding up cannot be expected. Therefore, a high-sensitivity amplifier consisting of a flip-flop has been considered as a sense circuit. That is, a dummy cell is provided to obtain an output signal that serves as a reference for the level of the read voltage of the memory cell, and the difference between the outputs of a desired memory cell and the dummy cell is differentially amplified using a flip-flop.

SUMMARY OF THE INVENTION An object of the present invention is to provide a new differential read type semiconductor memory in which memory cell outputs can be read out with high sensitivity and which is easy to design.

Hereinafter, embodiments of the present invention will be described in detail with reference to the drawings.

FIG. 1 shows the structure of an embodiment of a semiconductor memory according to the present invention, in which a 4-bit memory cell M ₀₀
This is an example in which dummy memory cells DM ₀ and DM ₁ are connected to a memory array MA in which ~M ₁₁ are arranged.

In the figure, memory cells M ₀₀ to M ₁₁ configuring memory array MA are transistors Q ₁ to _{Q 3} , respectively.
digit sense lines D ₀ , D ₁ , read selection lines R ₀ , R ₁ and write selection lines W ₀ , W ₁
It is connected to the.

In addition, memory cells in each row of memory array MA
Dummy memory cells DM ₀ and DM ₁ are provided in common to M ₀₀ , M ₀₁ and M ₁₀ , M ₁₁ , and these dummy cells DM ₀ and DM ₁ include the aforementioned read selection line R ₀ and write selection line W ₀ . Digit sense line DS is connected.

Furthermore, the digit sense lines D ₀ and D ₁ are commonly connected to the digit sense line D via transistors Q _g1 and Q _g2 , and this line D is connected to a high-sensitivity sense line D made of a flip-flop that can detect minute voltage differences. Connected to one input terminal of amplifier SA. On the other hand, the digit sense line DS is connected to a digit sense line D via a transistor _Qgs , which is connected to the other input terminal of the sense amplifier SA. Furthermore, the digit sense lines D ₀ , D ₁ , DS, D, are connected to the power supply V _DD via transistors that are turned on by the precharge signal P.

Also, the gates of transistors Q _g1 and Q _g2 are
It is grounded via a transistor that is turned on by the precharge signal P, and the address decoder AD
It is connected to the. This address decoder AD starts operating in response to a chip select signal CS, and generates outputs according to an address A and a signal obtained by inverting address A by an inverter 1.

Here, it is assumed that the dummy cells DM ₀ and DM ₁ have the following operating conditions. That is, the dummy cells DM ₀ and DM ₁ contain stored information such that when the digit sense line DS is charged to a high level voltage by precharging and then read out, the line DS always discharges toward a low level. This means that “1” is written in it. This is a dummy cell
This can be easily realized because it is sufficient to always write only "1" to DM ₀ and DM ₁ via the transistor Q _gs . Note that the write circuit portion is omitted in FIG. Furthermore, as shown in Fig. 2, when information of "1" and "0" is read from memory cells _M00 to _M11 , the time variation of both voltages on the digital sense lines D0 _{and D1} is approximately The conductance gm of the memory cells M ₀₀ to M ₁₁ and the dummy cells DM ₀ to _{DM 1} are made different so that the voltage of the digit sense line DS changes at an intermediate level. To explain more specifically, if memory cell M ₀₀ is selected, when the value stored by the gate capacitance of transistor Q ₂ is "1", transistor Q ₂ is turned on, so that the digital sense line D The _zero charge is discharged through transistors _Q1 and _Q2 . The time constant at this time is transistor Q ₁
and _Q2 are predetermined by the conductance of the series path. When the stored value is "0", transistor _Q2 is off and does not perform a discharging operation. As is well known, the conductance of a transistor can be determined in advance by changing the channel length and channel width of the gate. On the other hand, the transistor configuration on the dummy cell DM ₀ side is the same, but the two transistors _{Q 1 ,}
The series path conductance of the two transistors corresponding to these transistors is different from the series path conductance of Q ₂ , so when discharging the charge on the digit sense line DS through the transistor of dummy cell DM ₀ , The time constant is made to be different from that of memory cell M ₀₀ , thereby making it possible to cause a voltage change as described above.

Consider the case where the memory cell M ₀₀ is read in a state where the above conditions are satisfied (FIGS. 3 and 4). In the circuit shown in Figure 1, if the memory cell
If the information on M ₀₀ is "0", the digit sense lines D ₀ and D as shown in FIG. 3 remain at high level,
On the other hand, DS discharges towards a low level. When the set signal SET is applied to the sense amplifier SA at a certain appropriate level, the digit sense line DS is quickly discharged to a low level by the sense amplifier SA. At this time, the digital sense line
D ₀ and D are maintained at substantially high level voltages. On the other hand, if memory cell M ₀₀ has “1” information, the set signal
When SET is applied, the digit sense lines D ₀ and D go low, and the digit sense line DS is held high, as shown in FIG. From the above, depending on the information stored in memory cell M ₀₀ , line D
It can be seen that the voltage is maintained at a high pressure level according to the information at high speed.

FIG. 5 is another embodiment of the memory of the present invention that effectively uses a high sensitivity sense amplifier. In the example of FIG. 1, the load capacitance of line D viewed from sense amplifier SA becomes unbalanced. i.e. transistor
The capacitance on the digit sense line D side of Q _g1 and Q _g2 is larger than that on the transistor Q _gs side, causing a capacitance unbalance. dummy cell DM ₀ ,
The disadvantage is that memory design is difficult because the optimum gm ratio of DM ₁ and memory cells M ₀₀ to _{M 11} is directly related to the unbalanced degree of the load capacitance. In Fig. 5, in order to eliminate this drawback, the memory array MA shown in Fig. 1 is divided into two parts, and the output from the selected memory array MA1 or MA2 is connected to the unselected memory array MA2 or MA1. The output from the dummy cell DMC2 or DMC1 can be detected by the sense amplifier SA. In this example it is clear that the sense amplifier SA
From this point of view, the load capacitances are perfectly balanced, which makes designing the sense amplifier SA extremely easy.

In the figure, WD is a word driver, A ₀ , A ₂
is an address signal, _I0 to _I2 are inverters, _Cs is a chip select signal, and AND is an AND circuit.

As described above, according to the present invention, high-speed, highly integrated
It can be seen that it is possible to provide IC memory.

[Brief explanation of drawings]

FIG. 1 is a circuit diagram of an embodiment of a semiconductor memory according to the present invention, and FIG. 2 is a timing chart showing the relationship between the output level from a dummy cell and the output level from a memory cell. FIGS. 3 and 4 are diagrams showing the relationship between digit line voltages when the sense amplifier is set. FIG. 5 is a circuit diagram of another embodiment of the semiconductor memory according to the present invention. V _DD : Power supply voltage, P: Precharge signal, R ₀ ~
_R3 : Read selection line, _W0 to _W3 : Write selection line, M to M: Memory cell, _DM0 , _DM1 ,
DMC ₁ : DMC ₂ : Dummy cell, MA, MA1,
MA2: Memory array, D ₀ , D ₁ , DS, D,:
Digit sense line A, _A0 to _A2 : address,
1: Inverter, AD: Address recorder,
AND: AND circuit (decoder), CS: Chip select signal, SET: Set signal, SA: Sense circuit, Q _g1 to _{Q g3} : Sense gate transistor,
t: time, _tR : read start time, _ts : set time, V: voltage, WD: word driver.

Claims (1)

[Claims] 1. A plurality of memory cells, a dummy cell, and a differential amplifier that differentially detects a signal of a memory cell selected by a word selection signal among the plurality of memory cells and a signal of the dummy cell. A semiconductor memory comprising: a conductance of the memory cell and a conductance of the dummy cell. 2. A semiconductor memory having a plurality of memory cells, a dummy cell, and a differential amplifier that differentially detects a signal of a memory cell selected by a word selection signal among the plurality of memory cells and a signal of the dummy cell, Unlike the first digit sense line to which the memory cell is connected and the second digit sense line to which the dummy cell is connected, the first digit sense line is not connected to the dummy cell, and
A semiconductor memory characterized in that no memory cell is connected to the second digit sense line. 3. The semiconductor memory according to claim 2, wherein the memory cell and the dummy cell are connected to a word line to which the same signal is applied.