JPS62223889A - Booster circuit in semiconductor integrated circuit - Google Patents

Abstract

PURPOSE:To simultaneously boost stepwise so as to have a constant potential relation between nodes of more than two by connecting a capacitance respectively between the respective nodes of the nodes more than three on a semiconductor integrated circuit to form a capacitance connection circuit and applying different clock signals respectively to the respective nodes according to a constant time sequence. CONSTITUTION:When the second node and the third node are initially earthed, the first clock signal phi1 is applied to the first node, the capacitance CB1 is charged, the signal phi1 is separated, thereafter, the second clock signal phi2 is applied to the adjacent second node, and then, the first node is boosted by the capacitance connection between the two nodes and at the same time, the capacitance CB2 connected between the second node N2 and the third node N3 is charged. Then, after the signal phi2 is separated, the third clock signal phi3 is applied to the third node adjacent to the second node. The relation that the potential of the first node is higher than the potential of the second node is maintained.

Description

[Detailed Description of the Invention] [Purpose of the Invention (Industrial Application Field) The present invention relates to a booster circuit in a semiconductor integrated circuit such as a semiconductor memory, and particularly relates to a booster circuit in which two or more nodes have a constant potential relationship. The present invention relates to a voltage boosting circuit for simultaneously increasing voltage in stages.

(Prior Art) In semiconductor memories, an important issue is how stably information can be read and written. In particular, large-sized memories such as IM Bit Dynamic R
In AM (Random Access Memory), how stable and effective the bit line recharge is when reading and writing information is important in improving the circuit equalization margin. . However, in reality,
It cannot be said that this Priteyano operation necessarily operates with high reliability.

One of the reasons for this is the variation in the single-handedness of elements due to the miniaturization of design rules due to the recent technology of semiconductor devices.In other words, with the miniaturization, the circuit operating conditions have also changed. Differences in device characteristics between the devices and equipment can cause malfunctions.

Here, lM bit dynamic RA. The above problems will be explained in detail by taking the bit line precharge operation in M as an example. In a large capacity memory such as 1 Mbit, the number of memory cells connected to one bit line increases and the bit capacity fkCB increases, but the memory cells become smaller and the cell capacitance C8 decreases. There is a tendency to

Therefore, when Cσ6 decreases by 71%, the S/N ratio of the sense amplifier connected to the bit line deteriorates. In this trend, if the characteristics of the MOS transistor for bit precharge resistance vary due to the process, and a difference occurs in the charging ability for a pair of bit lines, a difference will occur in the charge level of the bit i pair, and the active This interferes with the operation of the sense amplifier during the operation period, and malfunction occurs in the sense operation.

On the other hand, if the time value of the pitch 0 preacher chisel flow is large, a large amount of power supply noise will be generated, so there is a need for a bit line equalize/precharge system that can suppress the generation of this power supply noise.

Therefore, the present inventor has proposed a method for precharging By}fl in stages B (bits devised a method to charge the battery in stages. That is, the paired bit lines BL. By first equalizing BL with an equalizing MOS transistor, 'A VCC potential (vc
C is set to precharge power supply potential), and then bit mBL is set using a precharge MOS transistor.

The idea is to charge each BL in stages to the vcc potential.

In this case, if we try to simply apply the above idea to the conventional equalize/precharge circuit, when the equalizing MOS transistor is in the equalizing operation period, the vcc level is added to its boot.
During this operation period, Pip} 49 BL, BL is dedicated. When the potential is raised to the vcc potential by precharging, the equalizing MOS transistor is turned off. In this case, the precharge MOS
The transistors are connected to the bit lines BLjff, each having one transistor.
Since the precharge MOS transistors are fflfied one by one, if there are variations in the characteristics of these precharge MOS transistors, especially in the inductance or threshold voltage of the transistors due to process variations, the equalization MOS transistors will be turned off as described above. Each pitch becomes
An unbalance occurs in the levels of iBL and R, resulting in malfunction of the sense amplifier, and the margin for circuit operation is significantly reduced. Therefore, it is necessary for the equalizing MOS transistor mentioned above to maintain two equalizing operation states even during the precharging operation by the runnostar, and for this purpose, the dirt potential of the precharging MO8) transistor must be stepped up. At the same time, the inventor of the present invention has devised that the gate potential of the equalizing MOS transistor should be stepped up so that it becomes higher than the dirt potential of the precharging MO8 transistor by a certain value or more.

In this case, it is desirable that a single configuration be simple as a step-up circuit to step-up the voltage so that the two nodes (the dirt of the grid charging transistor and the node of the equalizing transistor) have a constant potential relationship. .

(Problems to be Solved by the Invention) The present invention has been made in consideration of the above-mentioned circumstances, and has a simple configuration while having two or more nodes having a constant potential relationship. It is an object of the present invention to provide a booster circuit in a semiconductor integrated circuit which is capable of boosting the voltage simultaneously in stages and is effective when applied to a bit-win equalization/precharge circuit of a semiconductor memory.

[Structure of the Invention] (Means for Solving the Problems) The booster circuit in the semiconductor integrated circuit of the present invention is a capacitive coupling circuit in which capacitors are connected between each of three or more nodes on the semiconductor integrated circuit. , and different clock signals are applied to each of the nodes in a predetermined time order.

(Function) First, with the second node and the third node grounded,
A first clock signal φ1t- is applied to the node 1, and a capacitor 1c is connected between the first node N1 and the second node N.
After charging m1 and disconnecting the signal φ, the second clock signal φ, t- is applied to the adjacent second node. At the same time as the voltage is boosted, the second node N8 and the third node N,
The capacitor CB2 connected between the two is charged. Then the signal φ
, and then the third clock signal φ is applied to the 30th node of the second node ab. and the first node are simultaneously boosted.

In this case, the load capacitance connected to each node is
Determine i+1 t CB2.

This operation is performed in the same way as described above even when there are more nodes.

The above-mentioned booster circuit has a simple configuration, for example, in a bit equalize/precharge circuit of a semiconductor memory, the first node is connected to the r-to of the equalizing transistor, and the gate of the precharge transistor is connected to the first node. By connecting the nodes of the second volume, it is possible to charge the bit line pair stepwise to the same appropriate level. It is widely applicable to circuits.

(Example) Hereinafter, an example of the present invention will be described in detail with reference to the drawings.

In FIG. 1, N, , N, , N are the first . The second and third nodes are connected to the first capacitor CB1, and the first capacitor CB1 is connected to the node N, IN,14.

A second capacitor C12 is connected between N8, and the two capacitors fC111*C+2 are connected in series to form a capacitive coupling circuit. Each of the above nodes N1.

N,,N, have different first . Second. Third clock signal φ! ,φ,.

φ, corresponds to the first . Second. The clock signal is supplied from the third clock generation circuit 1, 2.3.

FIG. 2 is a timing waveform diagram showing the powerful operation of the booster circuit, in which the first clock signal φ1 rises at time t1, and at time t, which is delayed by the required time from t, the signal φ
, is disconnected from node N1 and the second clock signal φ,
When the voltage rises, the capacitive coupling due to the volume 1ci1 of the flute 1 increases the pressure at the first spinning node N,lσ by a predetermined pressure.

Next, a time t3 extending by 1tij m from the above t.
When the signal φ is disconnected from the node N1 and the third clock signal φ rises, the second node N3 is boosted by a predetermined voltage due to capacitive coupling by the second capacitor CB2. The first node N is boosted by a predetermined level due to capacitive coupling. That is, the third clock signal φ causes the second clock signal φ1 . The first clock signal φ1 is simultaneously boosted.

Therefore, according to the booster circuit, three nodes N,
Although it is a simple 45 configuration in which two capacitors Cm1aC112'i' are connected in series between , N, , Ns and different clock signals are inputted to each node at different timings, two nodes It becomes possible to increase the voltages in stages so that N, , N have a perfect potential relationship (a relationship in which the potential of the node N1 is always higher than the potential of the node N).

Note that by increasing the number of serial connections of capacitances and correspondingly increasing the number of clock signals, it becomes possible to step-up the voltages of three or more nodes so that they have a constant 11 ratio with each other.

Next, a case in which the above booster circuit is applied to a bit equalization/precharge circuit of a large-capacity dynamic RAM will be described with reference to FIGS. 3 and 4.

FIG. 3 shows a schematic configuration of a bit equalizer-precharge circuit, in which paired bit lines (BLS,
BLl), (BL2, BL2),...
....

Between (BL, BL,) are MOS for equalization.
) The transistors T, . . .
n and 暉.

BL2. -..., BL are connected to one end of a precharge MOS transistor T, -... and T, -, respectively, and these transistors T, -.

The other ends of T, . . . are connected to the vcc power supply node. And the equalizing transistor T,...
The equalization signal faLE common to each dart and the precharging transistors T, . . . , T, .
・Precharge 1g line L commonly attached to each dirt
1'i, and a first capacitor cB1 are connected between the first and second capacitors P, the equalize signal line LE is connected to the output node N1 of the first clock generation circuit 1, and the precharge signal gLP is connected to the first capacitor cB1. ah is applied to the output node N of the clock generation circuit 2 of No. 2. Further, a second capacitor CB2 is connected between the precharge signal iLP and the output node N of the third clock generation circuit 3.

FIG. 4 is a timing waveform diagram showing the operation of the above circuit.Due to the active operation of the memory cycle, the potential of each bit line pair (represented by BL, BL) changes so that one bit line is at logic "'1" ( VC, 'at position), and the other no hit iiz logic becomes O- (ground potential),
The equal force precharge operation starts from this state. First, at time t1, the output clock of the first clock generation circuit 1 is output.

When φ1 rises to the ground potential vcct, the equalizing transistors T1... are turned on, and the bit line pair BL and BL are at the same potential vvcci! 6th place,
At time t, the output clock φ of the first clock generation circuit 1
, is disconnected from the first node N1, and at the same time, the output clock φ, of the second clock generation circuit 2 is lowered from the ground potential to vc.
When the voltage rises to c potential, the precharging transistor T
,...

T, -... are each driven on, and Viatro vs. BL
, BL is charged and the potential of each becomes "Cl knee" T
B (v, yo are the above MOS) transistor rq * z
pressure). At the same time, the node N1 is boosted by capacitive coupling by the first capacitor cs1, and the dirt potential of the equalizing transistor T1 is kept at a threshold voltage of 79 or higher than the potential of the bit line pair BL, BL. The equalized state is maintained.Next, at time t, the output clock φ of the second clock generation circuit 2 is disconnected from the second node N, and at the same time, the output clock φ of the third clock generation circuit 30 is grounded. When the potential rises from the potential to about vcct, the node N is boosted to the vcc potential or higher due to capacitive coupling by the second capacitor tci+2, and the grid-charging transistors T8..., T,... continue to operate in the grid-charging state. At the same time, the node N1 is further boosted by capacitive coupling by the capacitor ff1cB1 of $1, and the l'-) potential of the equalizing transistor T1... becomes vcc.
Since the voltage is maintained at 10 V□ or more, the equalized state is maintained, and bits a and BL and TI'L are charged to the same vcc potential. After the bit lines are equalized and precharged in this way, the clock φ,.

φ, are read back to the respective nodes N,,N,,
The clocks φ1, φ8. .phi., falls to the ground potential, after which the memory cell selection operation starts as usual, and word selection is performed.

In the bit line equalization/precharge operation described above, the boost ratio (bootstrap ratio) is as follows. Now, the equalizing transistor T per chip...
The total dirt capacity of ・Ce.

The total capacitance of the precharge transistors T, . . . , T, . . is Cp, the first capacitance fiCB, and the second capacitance i.
c, bootstrap ratio of 2 β1, respectively.

Since the clock φ□ is boosted by the clock φ, denoted by β, attention is paid to the circuit portion connected to the nodes N, ,N. The clock φ is boosted by the clock φ, but the first
This is because the capacitor Ce of ff-) is connected through the capacitor Cl11t-. Therefore, due to the clock φ, the node N,
is β! The voltage is boosted by ×vCC, and node N8 becomes β, ×β,
The voltage will be increased by xvcc. In this case, in order to maintain the equalizing transistor T□...'s rising operation state, the boosted voltage of the node N, β1×β, Xvcc
However, it is necessary to set the equalizing transistors T, .

In the above-mentioned BitMori equalize/precharge circuit, it is desirable from the viewpoint of circuit flexibility that the boosting of the equalize signal line LE due to capacitive coupling between nodes N, N1 is performed almost equally within the memory cell array. C11/64 may be formed so that the first capacitor C1 is divided and arranged within the memory cell array. That is, when the memory cell array on the chip is divided into four pieces by dividing into 4 x 16, for example, C11/64 It is only necessary to form a capacitance of the size of 64 in each section. In this way, the degree of freedom in pattern design of the memory cell array is improved, and the circuit surface size can be reduced.If C11 were to be formed as a single capacitor, the pattern area would become extremely large, making it unusable. It becomes a target and the problem is solved.

In addition, each capacitor in the above embodiment may have a :vlO8 (insulated r-) type structure, or a linear structure (for example, an aluminum film and a polysilicon layer in an insulating layer, or a first layer of aluminum film and a polysilicon layer). (opposed to the second layer of aluminum film) may also be used.

According to the above-mentioned higher voltage booster circuit and higher voltage bit line equalization/precharge circuit, even if there are differences in characteristics such as the threshold voltage of MO8) transistors for charging due to variations in process conditions, the bit line BL ,BL
are charged to the same level, so that the sensing operation of the sense amplifier is performed stably when reading memory cell data (C), and the margin of sensing operation is greatly improved.In other words, the margin of sensing operation is greatly improved. In response to process constraints associated with higher integration of memory, circuit technology has been applied as described above.

This can be effectively dealt with by setting the BLs at equal ζ positions. In addition, by using the above-mentioned sophisticated booster circuit, the booster circuit required in the conventional equalize/precharge signal generation circuit for driving the equalize number precharge transistor is not required, and the node booster circuit is not required. Since the capacitive coupling capacitor can be divided and arranged within the memory cell array, the area occupied by the booster circuit on the step can be reduced. This will be very effective in promoting higher integration and higher performance of memory.

[Effects of the Invention] As described above, according to the booster circuit in the semiconductor integrated circuit of the present invention, the configuration is simple and it is possible to simultaneously boost the voltages of two or more nodes in a stepwise manner so that they have a certain positional relationship. This makes it possible to effectively apply this method to bit gland equalization/precharge circuits of semiconductor memories.

[Brief explanation of drawings]

FIG. 1 is a configuration explanatory diagram showing one embodiment of a booster circuit in a semiconductor integrated circuit of the present invention, FIG. 2 is a timing waveform diagram showing the operation of the circuit of FIG. 1, and FIG. 3 is an example of application of the present invention. FIG. 4 is a timing waveform diagram showing the operation of the circuit shown in FIG. 3. N,,N,IN,--Node, C111e C12
... Capacity, φ1, φ! , φ3... Clock signal, T1... MO8) transistor for equalization, T...
T,... MO3) transistor for precharging, LE
... Equalize signal line, LP - ... Precharge signal door, BL. BLl#”' BLn* Bl-...Bit line,
1, 2, 3--Clock generation circuit. Figure 1 Figure 2 1t2t3 Figure 4

Claims (6)

[Claims] (1) A capacitive coupling circuit in which a capacitor is connected between each of three or more nodes on a semiconductor integrated circuit;
1. A booster circuit for a semiconductor integrated circuit, comprising a circuit that applies different clock signals to each of the nodes in a predetermined time order. (2) the nodes are first, second, and third nodes;
A first clock signal, a second clock signal, and a third clock signal correspond to the first node, second node, and third node.
2. A booster circuit in a semiconductor integrated circuit according to claim 1, wherein the booster circuit is configured to sequentially input the clock signals of . (3) Applying the potential of the second node and the potential of the first node to the gates of different MOS transistors,
When the corresponding MOS transistor is turned on by the potential of the node, the boosted potential of the first node is always higher than the potential of the second node.
Claim 2 characterized in that the value of the capacitance between the first node and the second node and the value of the capacitance between the second node and the third node are set. A booster circuit in the semiconductor integrated circuit described in 2. (4) The MOS transistors whose gates are respectively supplied with the potential of the first node and the potential of the second node are equalizing transistors and precharging transistors corresponding to each bit line pair of the memory cell array in the dynamic memory. Claim 1, wherein the bit line pair is brought into the same potential state by the equalizing transistor, and then the bit line pair is precharged in stages until the bit line pair reaches approximately the precharge power supply voltage. A booster circuit in the semiconductor integrated circuit according to item 3. (5) The boosting voltage in the semiconductor integrated circuit according to claim 4, wherein the capacitance between the first node and the second node is divided and arranged in the memory cell array. circuit. (6) A booster circuit in a semiconductor integrated circuit according to any one of claims 1 to 5, wherein the capacitor has a MOS structure or a linear structure.