JPS5580922A - Complementary mos logic circuit - Google Patents

Complementary mos logic circuit

Info

Publication number
JPS5580922A
JPS5580922A JP15520178A JP15520178A JPS5580922A JP S5580922 A JPS5580922 A JP S5580922A JP 15520178 A JP15520178 A JP 15520178A JP 15520178 A JP15520178 A JP 15520178A JP S5580922 A JPS5580922 A JP S5580922A
Authority
JP
Japan
Prior art keywords
turned
mosfet
logic circuit
time
fet26
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP15520178A
Other languages
Japanese (ja)
Other versions
JPS5945296B2 (en
Inventor
Toshiyuki Araki
Isato Kazama
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Mitsubishi Electric Corp
Original Assignee
Mitsubishi Electric Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Mitsubishi Electric Corp filed Critical Mitsubishi Electric Corp
Priority to JP53155201A priority Critical patent/JPS5945296B2/en
Publication of JPS5580922A publication Critical patent/JPS5580922A/en
Publication of JPS5945296B2 publication Critical patent/JPS5945296B2/en
Expired legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K19/00—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
    • H03K19/02—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components
    • H03K19/08—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components using semiconductor devices
    • H03K19/094—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components using semiconductor devices using field-effect transistors
    • H03K19/0944—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components using semiconductor devices using field-effect transistors using MOSFET or insulated gate field-effect transistors, i.e. IGFET
    • H03K19/0948—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components using semiconductor devices using field-effect transistors using MOSFET or insulated gate field-effect transistors, i.e. IGFET using CMOS or complementary insulated gate field-effect transistors

Landscapes

  • Engineering & Computer Science (AREA)
  • Power Engineering (AREA)
  • Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Computing Systems (AREA)
  • General Engineering & Computer Science (AREA)
  • Mathematical Physics (AREA)
  • Logic Circuits (AREA)

Abstract

PURPOSE:To realize a logic circuit featuring a high-speed transition time as well as a small occupied chip area by securing the vertical connection between one unit of P-channel MOSFET and N-units of N-channel MOSFET. CONSTITUTION:Gate Q of each MOSFET is connected to the flip-flop of the N- notation. For example, if set side terminals Q3, Q4 and Q5 feature the high voltage, the high voltage is applied to the gates of PMOSFET25 plus NMOSFET26, 27 and 28 each. As a result, FET25 is off with FET26, 27 and 28 turned on respectively. At the same time, output connection point 33 features the low voltage, and FET26 is turned on. At the time during which output point 34 transfers, NMOSFET22, 23 and 24 are turned on. After this, PMOSFET29 and 30 are turned on, and this time is proportional to the chip size of MOSFET. In this connection, the overall chip size is reduced since the number of chips is small for the structure FET.
JP53155201A 1978-12-15 1978-12-15 Complementary MOS logic circuit Expired JPS5945296B2 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP53155201A JPS5945296B2 (en) 1978-12-15 1978-12-15 Complementary MOS logic circuit

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP53155201A JPS5945296B2 (en) 1978-12-15 1978-12-15 Complementary MOS logic circuit

Publications (2)

Publication Number Publication Date
JPS5580922A true JPS5580922A (en) 1980-06-18
JPS5945296B2 JPS5945296B2 (en) 1984-11-05

Family

ID=15600699

Family Applications (1)

Application Number Title Priority Date Filing Date
JP53155201A Expired JPS5945296B2 (en) 1978-12-15 1978-12-15 Complementary MOS logic circuit

Country Status (1)

Country Link
JP (1) JPS5945296B2 (en)

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS58196729A (en) * 1982-05-11 1983-11-16 Matsushita Electric Ind Co Ltd C-mos multiinput gate circuit
JPS626532A (en) * 1985-07-02 1987-01-13 Matsushita Electric Ind Co Ltd Multi-input cmos gate circuit

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS58196729A (en) * 1982-05-11 1983-11-16 Matsushita Electric Ind Co Ltd C-mos multiinput gate circuit
JPH0432572B2 (en) * 1982-05-11 1992-05-29
JPS626532A (en) * 1985-07-02 1987-01-13 Matsushita Electric Ind Co Ltd Multi-input cmos gate circuit

Also Published As

Publication number Publication date
JPS5945296B2 (en) 1984-11-05

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