JPS57106238A - Semiconductor logical integrated circuit device - Google Patents

Semiconductor logical integrated circuit device

Info

Publication number
JPS57106238A
JPS57106238A JP55182344A JP18234480A JPS57106238A JP S57106238 A JPS57106238 A JP S57106238A JP 55182344 A JP55182344 A JP 55182344A JP 18234480 A JP18234480 A JP 18234480A JP S57106238 A JPS57106238 A JP S57106238A
Authority
JP
Japan
Prior art keywords
clock
flip
external
integrated circuit
test
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP55182344A
Other languages
Japanese (ja)
Inventor
Kanji Hirabayashi
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Toshiba Corp
Original Assignee
Toshiba Corp
Tokyo Shibaura Electric Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Toshiba Corp, Tokyo Shibaura Electric Co Ltd filed Critical Toshiba Corp
Priority to JP55182344A priority Critical patent/JPS57106238A/en
Publication of JPS57106238A publication Critical patent/JPS57106238A/en
Pending legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K21/00—Details of pulse counters or frequency dividers
    • H03K21/40—Monitoring; Error detection; Preventing or correcting improper counter operation

Landscapes

  • For Increasing The Reliability Of Semiconductor Memories (AREA)
  • Tests Of Electronic Circuits (AREA)
  • Techniques For Improving Reliability Of Storages (AREA)
  • Test And Diagnosis Of Digital Computers (AREA)
  • Bipolar Integrated Circuits (AREA)

Abstract

PURPOSE:To obtain a semiconductor logical integrated circuit which is so constituted as easy to test, by providing a switch logical operation circuit which removes restriction conditions on a clock from the external even if a flip-flop which cannot be controlled by the clock from the external is included. CONSTITUTION:An AND gate G13 which controls the input of a clock 1 by an external switch signal is provided additionally besides clock and data switching gates in a switch logical operation circuit where plural master-slave flip-flop units are cascaded to constitute a shift register. In case the test mode is set, the switch signal is set to 0 to constitute the shift register with flip-flops cascaded independently of the clock 1, and a clock 2 and data 2 are used to execute the circuit test. In case the normal operation mode is set, the switch signal is set to 1, and the clock 2 is set to 0.
JP55182344A 1980-12-23 1980-12-23 Semiconductor logical integrated circuit device Pending JPS57106238A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP55182344A JPS57106238A (en) 1980-12-23 1980-12-23 Semiconductor logical integrated circuit device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP55182344A JPS57106238A (en) 1980-12-23 1980-12-23 Semiconductor logical integrated circuit device

Publications (1)

Publication Number Publication Date
JPS57106238A true JPS57106238A (en) 1982-07-02

Family

ID=16116659

Family Applications (1)

Application Number Title Priority Date Filing Date
JP55182344A Pending JPS57106238A (en) 1980-12-23 1980-12-23 Semiconductor logical integrated circuit device

Country Status (1)

Country Link
JP (1) JPS57106238A (en)

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS6120143A (en) * 1984-07-06 1986-01-28 Nec Corp Scannable latch circuit
JPH0290075A (en) * 1987-10-07 1990-03-29 Xilinx Inc System for scanning test of logical circuit

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS6120143A (en) * 1984-07-06 1986-01-28 Nec Corp Scannable latch circuit
JPH0463415B2 (en) * 1984-07-06 1992-10-09 Nippon Electric Co
JPH0290075A (en) * 1987-10-07 1990-03-29 Xilinx Inc System for scanning test of logical circuit

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