JPS6120143A - Scannable latch circuit - Google Patents

Abstract

PURPOSE:To make it possible to mix a latch circuit simply with a flip-flop (FF) by latching a main latch circuit and a sub-latch circuit at the leading edge and trailing edge of a data set pulse, delaying input data to the main latch circuit and outputting the data from the sub-latch circuit. CONSTITUTION:The main latch circuit 1 stores input data 104 at the leading edge of a data set pulse 103, and after holding the data 104 until the succeeding leading edge, outputs data 105. The circuit 1 outputs the output signal 105 to the sub-latch circuit 2 at the trailing edge of the pulse 103 to make the circuit 2 latch the signal 105 until the succeeding trailing edge and inputs a scan data signal 101 or a data signal as input data 104 in accordance with the ''1'' of ''0'' of a scan specifying signal 100. When the signal 100 is ''1'', the circuit 1 inputs the signal 101 and outputs the output data 105 to the circuit 2 at the leading edge of the pulse 103 and the circuit 2 sets up the input signal 105 at the trailing edge of the pulse 103, and after holding the contents until the succeeding trailing edge of the pulse 103, outputs a signal to a scan data output terminal 107.

Description

TECHNICAL FIELD The present invention relates to a scannable latch circuit that can be inserted into a scan path in a data processing device.

Conventional technology When configuring a scan path in a data processing device in which flip-flop circuits and latch circuits coexist, the flip-flop circuit and latch circuit in the processing device configure separate scan paths, and the two scan paths described in It is necessary to connect between them by a separate circuit to prevent racing. This is because when the output of a latch circuit is connected to a flip-flop circuit, the latch output is immediately set to the flip-flop in the next stage, causing racing. It is not allowed to configure
Therefore, there is a drawback that the structure of the scan canvas is restricted and becomes complicated.

OBJECTS OF THE INVENTION It is an object of the present invention to overcome the above-mentioned drawbacks of the prior art without adding a separate circuit for anti-racing IE.

To provide a scannable latch circuit in which a latch circuit can be easily mixed with a flip-flop.

Structure of the Invention The scannable latch circuit of the present invention includes a main latch circuit that latches input data or scan data by the leading edge of the data set pulse, and latches the output data of the main latch circuit by the trailing edge of the data set pulse. and a sub latch circuit, the scan data input to the main latch circuit is delayed and outputted from the sub latch circuit.

Embodiments of the Invention Next, the present invention will be described in detail with reference to the drawings.

FIG. 1 is a block diagram showing one embodiment of the present invention.

That is, the falling edge (leading edge) of the data set pulse 103
The main latch circuit 1 stores and outputs the input data 104, and holds and outputs the input data until the next falling edge of the data set pulse 103, and the output data 10 of the main latch circuit l.
5 and the rising edge of the data set pulse +03 (
a sub-latch circuit 2 which outputs data to the scan data output terminal 107 according to the trailing edge) and latches it until the next rising edge of the data set pulse 103; an AND gate 11 which is opened by the scan instruction signal 100 and allows the scan data signal +01 to pass through; The scan instruction signal 100 is inverted by an inverting circuit 10.
Data signal 1 is opened by a signal inverted by
An 1 gate 12 that allows 02 to pass through, and an AND gate 1
The output of 1 or 12 is the input data to the main latch circuit 1!
04 and an OR circuit 13 which supplies the main latch circuit l.

When the scan instruction signal +00 is 0'', the AND gate 11 is closed, the AND gate 12 is open, and the data signal 102 is connected to the AND gate 12 and the OR circuit 13.
It is input to the main latch circuit l through.

A normal latch operation is performed in which the data set pulse +03 is set in the main latch circuit 1 and output to the data output terminal 10B at the fall of the data set pulse +03.

When the scan instruction signal 100 is °1n, the AND gate 11 opens and the AND gate 12 closes, so the scan data signal +01 is input to the main latch circuit l via the AND gate 11 and the OR circuit 13, and the main latch When the data set pulse 103 falls, the circuit 1 outputs the input data 104 as data 105 to the data output terminal 108 and inputs it to the sub latch circuit 2. At the rising edge of the data set pulse 103, the sub latch circuit 2 sets the output data 105 of the main latch circuit and outputs it to the scan data output terminal +07, and its contents are held until the next rising edge of the data set pulse 103.

FIG. 2(A) is a time chart showing the data set pulse 103, and FIG. 2(B) and (C) are time charts showing the states of the main latch circuit 1 and the sub latch circuit 2, respectively. That is, data set pulse +0
When the data set pulse 103 is at a low level, the main latch circuit I is in a through state and outputs the input data as it is, but when the data set pulse 103 is at a high level, it is in a holding state and outputs the input data as it is. During this period, the data input to the main latch circuit l is ignored, and when the main latch circuit l enters the through state at time S due to the next fall of the data set pulse 103, the output data 105
The input data at time S is held and output through the period ta in the through state and the period tA in the holding state.

On the other hand, as shown in FIG. 2C, the sub latch circuit 2 is in a holding state when the data set pulse 103 is at a low level, and enters a through state when the data set pulse 103 is at a high level. Therefore, in the through state from the rising edge of the trailing edge of the data set pulse 103 at time s-1 to the falling edge at time S and the subsequent holding state period 〇', a holding output is output to the main latch circuit l at time s-1. The output data of the main latch circuit l is outputted to the scan data output terminal 107, and the output data of the main latch circuit l is outputted to the scan data output terminal 107. This state is maintained during the period tB until the next rise. Therefore, the sub latch circuit 2
is the data set pulse 10 for the peak signal of the main latch circuit l.
The scan data output terminal 1 is delayed by the pulse width of 3.
It will be output on 07. Therefore, if a scan path is configured by inputting the scan data output terminal 107 to a similar latch circuit or flip-flop circuit in the next stage, racing will not occur. This means that when the main latch circuit l enters the through state at time S, the sub latch circuit 2 is in the holding state, and is input to the main latch circuit l at time s-1 and held in the main latch circuit l until time S. This is because the previous scan data signal that was being held is held and outputted, and the flip-flop or latch circuit at the next stage, at the falling edge of the data set pulse 103 at time S,
This is because the data held by the main latch circuit l is held by the data set pulse 103 at time s-1.

A latch circuit having a plurality of data input terminals and a data set terminal, or a latch circuit having a reset terminal can also be inserted into the scan path by connecting a similar sub-latch circuit.

Effects of the Invention As described above, in the present invention, the output of the main latch circuit is connected to the input of the sub latch circuit, and the sub latch circuit holds and outputs the output data of the main latch circuit according to the trailing edge of the data set pulse. Therefore, at the leading edge of the data set pulse, the scan data held in the main latch circuit by the previous data set pulse is held and output. Therefore, by connecting the output of the sub-latch circuit to the input of a subsequent flip-flop or similar latch circuit, the function of the normal latch circuit is not lost, and a separate path for racing protection II is not provided. This has the effect that it is possible to easily form a scan path in which flip-flop circuits and latch circuits are mixed.

[Brief explanation of drawings]

Figure 1 is a circuit diagram showing an embodiment of the present invention, Figure 2 (A)
, (B) and (C) are time charts showing the data set pulse and the states of the main and sub latch circuits, respectively, in the above embodiment. In the figure, 1: main latch circuit, 2: sub latch circuit, l
O: inversion circuit, 100 Niscan instruction signal, 101 Niscan data signal, 102: data signal, IO2: data set pulse, 104: input data, 105: output data, 106: data output terminal, 107: scan data output terminal.

Claims (1)

[Claims] The main latch circuit comprises a main latch circuit that latches input data or scan data by a leading edge of a data set pulse, and a sub latch circuit that latches output data of the main latch circuit by a trailing edge of the data set pulse. 1. A scannable latch circuit, wherein scan data inputted to the sub latch circuit is delayed and outputted from the sub latch circuit.