JPS6442920A - Ring counter - Google Patents

Ring counter

Info

Publication number
JPS6442920A
JPS6442920A JP19944587A JP19944587A JPS6442920A JP S6442920 A JPS6442920 A JP S6442920A JP 19944587 A JP19944587 A JP 19944587A JP 19944587 A JP19944587 A JP 19944587A JP S6442920 A JPS6442920 A JP S6442920A
Authority
JP
Japan
Prior art keywords
state
flip
flop
stage
clock
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP19944587A
Other languages
Japanese (ja)
Other versions
JPH0630442B2 (en
Inventor
Toru Kosugi
Takahiro Furukawa
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Fujitsu Ltd
Original Assignee
Fujitsu Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Fujitsu Ltd filed Critical Fujitsu Ltd
Priority to JP19944587A priority Critical patent/JPH0630442B2/en
Publication of JPS6442920A publication Critical patent/JPS6442920A/en
Publication of JPH0630442B2 publication Critical patent/JPH0630442B2/en
Anticipated expiration legal-status Critical
Expired - Lifetime legal-status Critical Current

Links

Landscapes

  • Manipulation Of Pulses (AREA)

Abstract

PURPOSE:To attain a stable operation at high speed by synchronizing the input state of the 1st stage flip flop of a pulse generating means with a clock taking the operation timing and setting up it by the next clock when the output state of the setup time setting means is changed. CONSTITUTION:A pulse generating means 10 being N-stage of cascade connection of a positive output of a 1st flip-flop storing a binary state is given to the input of a 2nd flip-flop storing the binary state, an initial state setting means 20 where a positive output of the N-stage of flip-flops constituting the pulse generating means 10 and its inverted output and a clock having prescribed speed are operated logically so as to set the initial state of the 1st stage flip-flop at a constant state at all times, and a setup time setting means 30 are provided. Then the flipflop is set up at the leading edge of the clock CLK after one period from the time when the input state of the 1st stage flip-flop is decided. Thus, the counter is miniaturized and stable operation is attained even at power application and high speed processing is made possible.
JP19944587A 1987-08-10 1987-08-10 Ring counter Expired - Lifetime JPH0630442B2 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP19944587A JPH0630442B2 (en) 1987-08-10 1987-08-10 Ring counter

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP19944587A JPH0630442B2 (en) 1987-08-10 1987-08-10 Ring counter

Publications (2)

Publication Number Publication Date
JPS6442920A true JPS6442920A (en) 1989-02-15
JPH0630442B2 JPH0630442B2 (en) 1994-04-20

Family

ID=16407933

Family Applications (1)

Application Number Title Priority Date Filing Date
JP19944587A Expired - Lifetime JPH0630442B2 (en) 1987-08-10 1987-08-10 Ring counter

Country Status (1)

Country Link
JP (1) JPH0630442B2 (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH04357190A (en) * 1991-06-03 1992-12-10 Komatsu Electron Metals Co Ltd Single crystal production apparatus

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH04357190A (en) * 1991-06-03 1992-12-10 Komatsu Electron Metals Co Ltd Single crystal production apparatus

Also Published As

Publication number Publication date
JPH0630442B2 (en) 1994-04-20

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