JPS5675743A - Frame clock pulse generating circuit - Google Patents

Frame clock pulse generating circuit

Info

Publication number
JPS5675743A
JPS5675743A JP15144979A JP15144979A JPS5675743A JP S5675743 A JPS5675743 A JP S5675743A JP 15144979 A JP15144979 A JP 15144979A JP 15144979 A JP15144979 A JP 15144979A JP S5675743 A JPS5675743 A JP S5675743A
Authority
JP
Japan
Prior art keywords
clock pulse
frame clock
generating circuit
pulse generating
time
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP15144979A
Other languages
Japanese (ja)
Inventor
Nobuhisa Kamoi
Masaaki Ogiso
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Fujitsu Ltd
Original Assignee
Fujitsu Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Fujitsu Ltd filed Critical Fujitsu Ltd
Priority to JP15144979A priority Critical patent/JPS5675743A/en
Publication of JPS5675743A publication Critical patent/JPS5675743A/en
Pending legal-status Critical Current

Links

Classifications

    • HELECTRICITY
    • H04ELECTRIC COMMUNICATION TECHNIQUE
    • H04LTRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L7/00Arrangements for synchronising receiver with transmitter

Landscapes

  • Engineering & Computer Science (AREA)
  • Computer Networks & Wireless Communication (AREA)
  • Signal Processing (AREA)
  • Time-Division Multiplex Systems (AREA)

Abstract

PURPOSE:To produce the frame clock pulse to a suitable position, by providing an FF which produces the frame clock pulse to the FF constituting n-stage self-start type ring counter. CONSTITUTION:By taking the input CL of a D-FF 301 from the output of a D-FF 103, the state of linking 8 sets of D-FF, for example, at the 12-th circulation of the 7-th phase clock pulse in the self-start type ring counter 100, is obtained. Accordingly, the propagation delya time which is the time required to become the waiting state of D-FF201 from the input CL of D-FF301 constituting the frequency dividing counter 300 via the frequency dividing circuit 302, NAND circuit 202, and inverter 203, is made shorter than one pulse time of the clock TC, allowing to pick up the frame clock pulse at a prescribed position from D-FF107.
JP15144979A 1979-11-22 1979-11-22 Frame clock pulse generating circuit Pending JPS5675743A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP15144979A JPS5675743A (en) 1979-11-22 1979-11-22 Frame clock pulse generating circuit

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP15144979A JPS5675743A (en) 1979-11-22 1979-11-22 Frame clock pulse generating circuit

Publications (1)

Publication Number Publication Date
JPS5675743A true JPS5675743A (en) 1981-06-23

Family

ID=15518831

Family Applications (1)

Application Number Title Priority Date Filing Date
JP15144979A Pending JPS5675743A (en) 1979-11-22 1979-11-22 Frame clock pulse generating circuit

Country Status (1)

Country Link
JP (1) JPS5675743A (en)

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