JPS5671350A - Clock pulse generating circuit - Google Patents

Clock pulse generating circuit

Info

Publication number
JPS5671350A
JPS5671350A JP14740179A JP14740179A JPS5671350A JP S5671350 A JPS5671350 A JP S5671350A JP 14740179 A JP14740179 A JP 14740179A JP 14740179 A JP14740179 A JP 14740179A JP S5671350 A JPS5671350 A JP S5671350A
Authority
JP
Japan
Prior art keywords
circuit
signal
clock pulse
phi1
input
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP14740179A
Other languages
Japanese (ja)
Inventor
Kenji Hashi
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
NEC Corp
Original Assignee
NEC Corp
Nippon Electric Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by NEC Corp, Nippon Electric Co Ltd filed Critical NEC Corp
Priority to JP14740179A priority Critical patent/JPS5671350A/en
Publication of JPS5671350A publication Critical patent/JPS5671350A/en
Pending legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L7/00—Arrangements for synchronising receiver with transmitter
    • H04L7/02—Speed or phase control by the received code signals, the signals containing no special synchronisation information
    • H04L7/027—Speed or phase control by the received code signals, the signals containing no special synchronisation information extracting the synchronising or clock signal from the received signal spectrum, e.g. by using a resonant or bandpass circuit

Abstract

PURPOSE:To enable to generate clock pulse less in the interference between codes with a simple constitution, by forming the timing component in combination with a delay line and an exclusive logical sum circuit. CONSTITUTION:An NRZ code phi1 input to a terminal 1 is distributed into two; one is fed to one input of an exclusive logic circuit 3 and another is delayed at a delay line 2 by the width of 1/2-bit and fed to another input terminal of the circuit 3 as a signal phi2. The output signal phi3 of the circuit 3 is fed to a resonance circuit 4 which takes the width of one bit of th signal phi1 as a period. Since the circuit 4 has higher Q, even if the input signal phi3 is intermittent to a certain degree, a continuous wave phi4 is obtained at the output of the circuit 4, and the signal phi4 is shaped at a wave shape circuit 5 to obtain a clock pulse phi5. The signal phi1 is read in from a latch circuit 6 in the clock pulse phi5, and the output is delivered to a terminal 7. The signal phi3 produces the timing component which drives the circuit 4 when the signal phi1 changes from high to low level and from low to high level.
JP14740179A 1979-11-14 1979-11-14 Clock pulse generating circuit Pending JPS5671350A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP14740179A JPS5671350A (en) 1979-11-14 1979-11-14 Clock pulse generating circuit

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP14740179A JPS5671350A (en) 1979-11-14 1979-11-14 Clock pulse generating circuit

Publications (1)

Publication Number Publication Date
JPS5671350A true JPS5671350A (en) 1981-06-13

Family

ID=15429446

Family Applications (1)

Application Number Title Priority Date Filing Date
JP14740179A Pending JPS5671350A (en) 1979-11-14 1979-11-14 Clock pulse generating circuit

Country Status (1)

Country Link
JP (1) JPS5671350A (en)

Cited By (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS61208318A (en) * 1985-03-08 1986-09-16 インターナシヨナル　コンピユーターズ　リミテツド Decoder for manchester coded data
JPH01284036A (en) * 1988-05-10 1989-11-15 Nec Corp Timing extracting circuit
JPH0392829A (en) * 1989-09-06 1991-04-18 Fujitsu Ltd Light clock signal extracting device
JPH03184438A (en) * 1989-12-13 1991-08-12 Matsushita Electric Ind Co Ltd Pre-processing circuit for clock extraction
JPH07303097A (en) * 1992-09-22 1995-11-14 Ind Technol Res Inst Clock regenerating circuit
WO2003005585A1 (en) * 2001-07-06 2003-01-16 Telefonaktiebolaget L.M. Ericsson A signal generator device, method for generating a signal and devices including such a signal generator device

Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS4856010A (en) * 1971-11-15 1973-08-07

Patent Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS4856010A (en) * 1971-11-15 1973-08-07

Cited By (9)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS61208318A (en) * 1985-03-08 1986-09-16 インターナシヨナル　コンピユーターズ　リミテツド Decoder for manchester coded data
EP0194385A2 (en) * 1985-03-08 1986-09-17 International Computers Limited Decoder for Manchester encoded data
JPH01284036A (en) * 1988-05-10 1989-11-15 Nec Corp Timing extracting circuit
EP0342010A2 (en) * 1988-05-10 1989-11-15 Nec Corporation Digital signal regenerator
US5197082A (en) * 1988-05-10 1993-03-23 Nec Corporation Digital signal regenerator
JPH0392829A (en) * 1989-09-06 1991-04-18 Fujitsu Ltd Light clock signal extracting device
JPH03184438A (en) * 1989-12-13 1991-08-12 Matsushita Electric Ind Co Ltd Pre-processing circuit for clock extraction
JPH07303097A (en) * 1992-09-22 1995-11-14 Ind Technol Res Inst Clock regenerating circuit
WO2003005585A1 (en) * 2001-07-06 2003-01-16 Telefonaktiebolaget L.M. Ericsson A signal generator device, method for generating a signal and devices including such a signal generator device

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