GB1398020A - Toggle flip-flop equivalent component - Google Patents

Abstract

1398020 Random number generators HEWLETT-PACKARD Ltd 16 Aug 1973 38940/73 Heading G4D [Also in Division H3] A toggle flip-flop equivalent component includes a storage element in the form of a flip-flop with a clock input C, Fig. lc, a non-gated feedback path Q, D and a data output Q connected such that the output changes its signal condition at every clock input signal and an inclusive OR- gate having its output connected to the clock input C of the storage element and, having one input connected to receive inverted input data DATA and another input connected to receive clock signals Co, whereby the output of the component changes its signal condition upon such clock signal, provided an inverted data signal is present at the one input, while the signal condition at the output is not changed when there is rio inverted data signal present at the one input. The toggle flip-flop uses a delay flip-flop. The introduction of the specification refers to known emitter coupled logic delay flipflops. Clock pulse shortening and delaying is provided by NOR gates 1, 2, 3 which provide delayed clock pulses to the inclusive OR gate of a predetermined width which is short relative to the width of the incoming pulses Co. An additional inclusive OR-gate may be provided between both branches of the clock gating circuit M and the other OR-gate. A 4-stage shift register generating pseudorandom binary sequences is disclosed, Fig. 2, including a toggle flip-flop equivalent component constituted by a delay flip-flop with non- gated feedback and a clock gating circuit M feeding three delay flip-flops where an inverted output of the last flip-flop stage feeds another clock input C2 of the toggle flip-flop. An edge with a positive slope will trigger the clock input C1 of the toggle flip-flop, provided a logical "0" is present at the other clock input C2.