KR890007402Y1 - Counter circuit with half duty cycle - Google Patents

Counter circuit with half duty cycle Download PDF

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Publication number
KR890007402Y1
KR890007402Y1 KR2019860021937U KR860021937U KR890007402Y1 KR 890007402 Y1 KR890007402 Y1 KR 890007402Y1 KR 2019860021937 U KR2019860021937 U KR 2019860021937U KR 860021937 U KR860021937 U KR 860021937U KR 890007402 Y1 KR890007402 Y1 KR 890007402Y1
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KR
South Korea
Prior art keywords
flip
clock
flop
input
output
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KR2019860021937U
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Korean (ko)
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KR880013931U (en
Inventor
최훈순
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삼성전자 주식회사
한형수
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Priority to KR2019860021937U priority Critical patent/KR890007402Y1/en
Publication of KR880013931U publication Critical patent/KR880013931U/en
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Publication of KR890007402Y1 publication Critical patent/KR890007402Y1/en

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    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K23/00—Pulse counters comprising counting chains; Frequency dividers comprising counting chains

Abstract

내용 없음.No content.

Description

반 듀티 사이클(Half Duty Cycle)을 갖는 카운터 회로Counter Circuit with Half Duty Cycle

제1도는 종래의 회로도.1 is a conventional circuit diagram.

제2도는 본 고안의 반듀티사이클(Half Duty Cycle)을 갖는 카운터 회로도.2 is a counter circuit diagram having a half duty cycle of the present invention.

제3도는 제2도의 타이밍도.3 is a timing diagram of FIG.

* 도면의 주요부분에 대한 부호의 설명* Explanation of symbols for main parts of the drawings

10 : 3개의 플립플롭 20 : 조합논리회로10: 3 flip-flops 20: Combination logic circuit

30 : 익스클루시브 오아(Exclusive-OR)게이트30: Exclusive-OR Gate

40 : D플립플롭40: D flip flop

본 고안은 문자체(Character Font)의 수평값에 따라 문자의 클럭 주기가 바뀌는 발광다이오드나 CRT조절기에 있어서 입력(I1, I2, I3)에 따라 4진에서 8진까지 프로그래머블(Programmable)한 카운터를 이용하고, 여러 가지 콘트롤 펄스(Control Pulse)를 쉽게 만들기 위해 하나의 플립플롭을 첨가해서 지연되어 오동작을 일으키는 것을 방지하여 안정된 동작을 수행하도록 하는 반 듀티 사이클(Half Duty Cycle)을 갖는 카운터 회로에 관한 것이다.The present invention is programmable from 4 to 8 digits according to inputs (I 1 , I 2 , I 3 ) in a light emitting diode or a CRT controller in which the clock period of the character changes according to the horizontal value of the character font. Counter circuit with half duty cycle that uses a counter and adds one flip-flop to make various control pulses easy to prevent delayed malfunction and perform stable operation It is about.

종래의 회로가 도시된 제1도를 참조하면, 입력(I1, I2, I3)은 조합논리 회로(20)의 입력에 연결되고, 조합 논리회로(20)의 출력은 문자클럭(Character Clock, Z)과 3개의 플립플롭(10)의 입력(In)과 익스클루시브오아(Exclusive-OR)게이트(30)의 입력에 클럭(Clock)이 연결되고, 출력은 3개의 플립플롭(10)의 클럭단자(CK)에 연결되며 3개의 플립플롭(10)의 출력(Out)은 조합논리회로(20)에 연결되었다.Referring to FIG. 1, which shows a conventional circuit, the inputs I 1 , I 2 , I 3 are connected to the input of the combinational logic circuit 20, and the output of the combinational logic circuit 20 is a character clock. Clock, Z) and the clock (Clock) are connected to the input (In) of the three flip-flop (10) and the input of the exclusive-OR gate 30, the output is three flip-flop (10) Is connected to the clock terminal CK, and the outputs of the three flip-flops 10 are connected to the combinational logic circuit 20.

제3도를 참조하면 I1, I2, I3-0, 0, 1 즉 5진 카운터일 경우에 제1도는 파형(Z)와 같은 출력을 얻어야 하나 실제로는 파형(W')처럼 되어 오동작인 경우의 클럭(A) 처럼 클럭(Clock)을 잃게 되어 출력은 파형(X)(전선부분까지)처럼 동작을 하고, 플립플롭(10)의 클럭을 조절하는 값(W)이 제3도에서 보는 바와 같이 td만큼 지연되어 오동작을 일으키게 된다.Referring to FIG. 3, in the case of I 1 , I 2 , I 3 -0, 0, 1, that is, a binary counter, FIG. 1 should obtain the same output as waveform Z, but it is actually like waveform W 'and malfunctions. The clock is lost like the clock A in case of, and the output operates like the waveform X (up to the front part), and the value W for adjusting the clock of the flip-flop 10 is shown in FIG. As you can see, there is a delay by td, which causes a malfunction.

본 고안은 상기한 문제점을 해결하기 위해 안출한 것으로, 종래의 회로도에 하나의 플립플롭을 첨가해서 정상 동작인 클럭과 같은 클럭을 얻어 안정된 반 듀티(Half Duty)의 문자클럭(Character Clock)을 얻어 필연적으로 생기는 지연시간(Delay time, td)줄이는데 본 고안의 목적이 있다.The present invention has been made to solve the above problems, and by adding one flip-flop to the conventional circuit diagram to obtain the same clock as the normal operation clock to obtain a stable half-duty character clock (Character Clock) The purpose of the present invention is to reduce the delay time (td) inevitably generated.

이하에 첨부된 제2도와 제3도를 참조하여 본 고안의 실시예를 설명한다.Hereinafter, an embodiment of the present invention will be described with reference to FIGS. 2 and 3.

제2도는 참조하면, 입력(I1, I2, I3)은 조합논리회로(20)의 입력에 연결되고 조합논리회로(20)의 출력은 3개의 플립플롭(30)의 입력(In)과 문자클럭(Z)과 플립플롭(40)의 입력(D)에 연결되며, 플립플롭(40)의 출력(Q)과 클럭단자(CK)에 연결된 클리어 단자(CL)는 함께 익스클루시브오아(Exclusive-OR) 게이트(30)의 입력에 연결되고, 익스클루시브오아(Exclusive-OR) 게이트(30)의 입력 출력은 3개의 플립플롭(10)의 클럭단자(CK)에 연결되며 3개의 플립플롭(10)의 출력(out)은 조합논리 회로(20)에 연결되었다.Referring to FIG. 2, inputs I 1 , I 2 , and I 3 are connected to the inputs of the combined logic circuit 20 and the outputs of the combined logic circuit 20 are inputs In of three flip-flops 30. And a clear terminal CL connected to the character clock Z and the input D of the flip-flop 40, and connected to the output Q of the flip-flop 40 and the clock terminal CK. (Exclusive-OR) is connected to the input of the gate 30, the input output of the Exclusive-OR gate 30 is connected to the clock terminal (CK) of the three flip-flop (10) The output of the flip-flop 10 is connected to the combinational logic circuit 20.

제2와 제3도를 참조하면 상기한 오동작을 방지하기 위해 파형(W)이 상태(C)에 나오도록 하지 않고 상태(b)에서 나오도록하면 즉, D플립플롭 (40)의 입력(D)의 파형이 제3도의 파형 (B)과 같다면, 플립플롭(40)의 출력(Q)이 파형(C)와 같은 파형을 얻게 되며 정상동작인 클럭(C)과 같은 클럭을 얻어 반 듀티(Half Duty)의 문자클럭(Character Clock)을 얻는다.Referring to FIGS. 2 and 3, in order to prevent the above malfunctioning, the waveform W does not come out of the state C, but leaves the state b, that is, the input D of the D flip-flop 40. If the waveform of) is the same as the waveform (B) of FIG. 3, the output Q of the flip-flop 40 obtains the same waveform as the waveform C, and obtains the same clock as the normal operation clock C to obtain the half-duty. Get a Character Clock of Half Duty.

즉 필연적으로 생기는 지연시간(td)에 의한 오동작을 막기 위해 파형(W)이 상태(b)에서 나오도록하여 (제3도의 파형(B)처럼), 플립플롭(40)의 입력(D)으로 입력시킨후 출력되는 파형(C) 처럼을 클럭의 로우레벨에서 클리어(qear)시키게 되어 결과적으로 파형(C) 처럼 지연시간(td)을 상당히 줄인 것이다.That is, in order to prevent the malfunction caused by the delay time td inevitably, the waveform W comes out of the state b (as in the waveform B of FIG. 3), and the input D of the flip-flop 40 After the input, the output waveform (C) is cleared at the low level of the clock (Qear). As a result, the delay time (td) is significantly reduced as the waveform (C).

상기한 본 고안은 한개의 D플립플롭을 첨가해서 지연 시간을 감소시켜 오동작을 방지하고, 클럭주파수를 로구성시 최대 4MHz 로 올릴 있으나 본 고안은 최대 10MHz이상으로 올릴 수 있다.The present invention described above can reduce the delay time by adding one D flip-flop to prevent malfunction, and increase the clock frequency to 4 MHz when configured as low, but the present invention can raise the maximum 10 MHz or more.

Claims (1)

3개의 입력(I1, I2, I3)과 3개의 플립플롭(10)의 출력(out)이 조합논리회로(20)의 입력에 연결되고, 출력은 문자클럭(Character Clock)와 3개의 플립플롭(10)의 입력(In)과 플립플롭(40)의 입력(D)에 연결되며, 플립플롭(40)의 출력(Q)와 함께 연결된 클럭단자(CK)와 클리어 단자(CL)는 익스클루시브오아(Exclusive-OR) 게이트(30)의 입력에 연결되고, 익스클루시브오아(Exclusive-OR) 게이트(30)의 출력은 3개의 플립플롭(10)의 클럭단자(CK)에 연결되어 필연적인 지연(td)을 줄여 오동작을 방지하는 것을 특징으로 하는 반 듀티 사이클(Half Duty Cycle)을 갖는 카운터 회로.The three inputs I 1 , I 2 , I 3 and the outputs of the three flip-flops 10 are connected to the inputs of the combined logic circuit 20, and the outputs are the character clock and the three clocks. The clock terminal CK and the clear terminal CL, which are connected to the input In of the flip-flop 10 and the input D of the flip-flop 40, are connected to the output Q of the flip-flop 40. The output of the exclusive-OR gate 30 is connected to the clock terminal CK of the three flip-flops 10, and the output of the exclusive-OR gate 30 is connected to the input of the exclusive-OR gate 30. Counter circuit having a half duty cycle, characterized in that to reduce the inevitable delay (td) to prevent malfunction.
KR2019860021937U 1986-12-30 1986-12-30 Counter circuit with half duty cycle KR890007402Y1 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
KR2019860021937U KR890007402Y1 (en) 1986-12-30 1986-12-30 Counter circuit with half duty cycle

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Application Number Priority Date Filing Date Title
KR2019860021937U KR890007402Y1 (en) 1986-12-30 1986-12-30 Counter circuit with half duty cycle

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KR880013931U KR880013931U (en) 1988-08-31
KR890007402Y1 true KR890007402Y1 (en) 1989-10-25

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Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US7505702B2 (en) 2005-09-29 2009-03-17 Samsung Electronics Co., Ltd. High power supply to control an abnormal load

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US7505702B2 (en) 2005-09-29 2009-03-17 Samsung Electronics Co., Ltd. High power supply to control an abnormal load
US7715738B2 (en) 2005-09-29 2010-05-11 Samsung Electronics Co., Ltd. High power supply to control an abnormal load

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