JPS55129998A - Transfer efficiency correcting circuit - Google Patents

Transfer efficiency correcting circuit

Info

Publication number
JPS55129998A
JPS55129998A JP3453379A JP3453379A JPS55129998A JP S55129998 A JPS55129998 A JP S55129998A JP 3453379 A JP3453379 A JP 3453379A JP 3453379 A JP3453379 A JP 3453379A JP S55129998 A JPS55129998 A JP S55129998A
Authority
JP
Japan
Prior art keywords
output
unit
waveform
clocks
circuit
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP3453379A
Other languages
Japanese (ja)
Inventor
Tsutomu Honma
Tetsuya Takahashi
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
NEC Corp
Original Assignee
NEC Corp
Nippon Electric Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by NEC Corp, Nippon Electric Co Ltd filed Critical NEC Corp
Priority to JP3453379A priority Critical patent/JPS55129998A/en
Publication of JPS55129998A publication Critical patent/JPS55129998A/en
Pending legal-status Critical Current

Links

Abstract

PURPOSE: To make it possible to correct tranfer efficiency at 100%, by making it possible to obtain the output after an infinitive time elapse by adding the output signal of a charge transfer unit and the delay signal to an operation circuit.
CONSTITUTION: The output signal of charge transfer unit 1 is held in sample hold dircuit 2 at the timing of transfer clocks c, and further, this output signal is held in sample hole circuit 3 at the timing of inversion clocks d of clocks c. Therefore, the output waveform of circuit 3 becomes a waveform which has the same form as the output of unit 1 and is delayed by one-period components of the transfer clock. This waveform is inputted to the inversion input terminal of operational amplifier 5, and at the same time, the output of unit 1 is inputted to the noninversion input terminal, and the output becomes output e after an infinitive time elapse for the step input of unit 1.
COPYRIGHT: (C)1980,JPO&Japio
JP3453379A 1979-03-23 1979-03-23 Transfer efficiency correcting circuit Pending JPS55129998A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP3453379A JPS55129998A (en) 1979-03-23 1979-03-23 Transfer efficiency correcting circuit

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP3453379A JPS55129998A (en) 1979-03-23 1979-03-23 Transfer efficiency correcting circuit

Publications (1)

Publication Number Publication Date
JPS55129998A true JPS55129998A (en) 1980-10-08

Family

ID=12416905

Family Applications (1)

Application Number Title Priority Date Filing Date
JP3453379A Pending JPS55129998A (en) 1979-03-23 1979-03-23 Transfer efficiency correcting circuit

Country Status (1)

Country Link
JP (1) JPS55129998A (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4672644A (en) * 1985-10-04 1987-06-09 Honeywell Inc. Compensator for charge transfer inefficiency in charge coupled devices

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4672644A (en) * 1985-10-04 1987-06-09 Honeywell Inc. Compensator for charge transfer inefficiency in charge coupled devices

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