JPS5689156A - Repeater for digital communication - Google Patents

Repeater for digital communication

Info

Publication number
JPS5689156A
JPS5689156A JP16722179A JP16722179A JPS5689156A JP S5689156 A JPS5689156 A JP S5689156A JP 16722179 A JP16722179 A JP 16722179A JP 16722179 A JP16722179 A JP 16722179A JP S5689156 A JPS5689156 A JP S5689156A
Authority
JP
Japan
Prior art keywords
circuit
delay
equalizer
discriminating
timing extracting
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP16722179A
Other languages
Japanese (ja)
Inventor
Takatoshi Minami
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Fujitsu Ltd
Original Assignee
Fujitsu Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Fujitsu Ltd filed Critical Fujitsu Ltd
Priority to JP16722179A priority Critical patent/JPS5689156A/en
Publication of JPS5689156A publication Critical patent/JPS5689156A/en
Pending legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L25/00—Baseband systems
    • H04L25/02—Details ; arrangements for supplying electrical power along data transmission lines
    • H04L25/20—Repeater circuits; Relay circuits
    • H04L25/24—Relay circuits using discharge tubes or semiconductor devices
    • H04L25/242—Relay circuits using discharge tubes or semiconductor devices with retiming

Abstract

PURPOSE:To prevent accumulation of jitter, by setting t1>>t2 or t1<<t2 when the delay time from the equalizer to the discriminating circuit and the delay time from the equalizer to the discriminating circuit through the timing extracting circuit are denoted as t1 and t2 respectively. CONSTITUTION:The digital signal is input to discriminating circuit 9 and timing extracting circuit 8 through equalizer 6. The output of timing extracting circuit 8 is input to discriminating circuit 9 through delay circuit 11. At this time, t1>>t2 or t1<<t2 is set when the signal delay time from equalizer 6 to discriminating circuit 9 and the signal delay time from equalizer 6 to discriminating circuit 9 through timing extracting circuit 8 and delay circuit 11 are denoted as t1 and t2 respectively. Thus, the recurrent action of systematic jitter is reduced by inserting delay circuit 11 to delay the clock signal by several time slots or more.
JP16722179A 1979-12-22 1979-12-22 Repeater for digital communication Pending JPS5689156A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP16722179A JPS5689156A (en) 1979-12-22 1979-12-22 Repeater for digital communication

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP16722179A JPS5689156A (en) 1979-12-22 1979-12-22 Repeater for digital communication

Publications (1)

Publication Number Publication Date
JPS5689156A true JPS5689156A (en) 1981-07-20

Family

ID=15845678

Family Applications (1)

Application Number Title Priority Date Filing Date
JP16722179A Pending JPS5689156A (en) 1979-12-22 1979-12-22 Repeater for digital communication

Country Status (1)

Country Link
JP (1) JPS5689156A (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5046185A (en) * 1988-09-03 1991-09-03 Hitachi, Ltd. Regenerative repeater

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5046185A (en) * 1988-09-03 1991-09-03 Hitachi, Ltd. Regenerative repeater

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