JPS5599650A - Integrated circuit - Google Patents

Integrated circuit

Info

Publication number
JPS5599650A
JPS5599650A JP692279A JP692279A JPS5599650A JP S5599650 A JPS5599650 A JP S5599650A JP 692279 A JP692279 A JP 692279A JP 692279 A JP692279 A JP 692279A JP S5599650 A JPS5599650 A JP S5599650A
Authority
JP
Japan
Prior art keywords
region
clock
speed process
speed
low
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP692279A
Other languages
Japanese (ja)
Inventor
Ryuichi Sato
Tomio Tanaka
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
NEC Corp
Original Assignee
NEC Corp
Nippon Electric Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by NEC Corp, Nippon Electric Co Ltd filed Critical NEC Corp
Priority to JP692279A priority Critical patent/JPS5599650A/en
Publication of JPS5599650A publication Critical patent/JPS5599650A/en
Pending legal-status Critical Current

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  • Executing Machine-Instructions (AREA)

Abstract

PURPOSE: To reduce furthermore the power consumption of the microprocessor using the complementary metal oxide semiconductor CMOS, by switching the internal clock velocity within the microprocessor between the high and low speeds.
CONSTITUTION: Fixed memory unit ROM program region is divided into region 1 requiring no high-speed process and region 2 requiring the high-speed process each for programming. When the process jumps from region 1 to 2, bit B is supplied through input terminal 14. Thus the basic clock of the external clock is selected to terminal 11 to perform the high-speed process. In case the jump is given from region 2 to 1, the low-speed clock in which the basic clock is divided is selected to terminal 11 to perform the low-speed process.
COPYRIGHT: (C)1980,JPO&Japio
JP692279A 1979-01-23 1979-01-23 Integrated circuit Pending JPS5599650A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP692279A JPS5599650A (en) 1979-01-23 1979-01-23 Integrated circuit

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP692279A JPS5599650A (en) 1979-01-23 1979-01-23 Integrated circuit

Publications (1)

Publication Number Publication Date
JPS5599650A true JPS5599650A (en) 1980-07-29

Family

ID=11651730

Family Applications (1)

Application Number Title Priority Date Filing Date
JP692279A Pending JPS5599650A (en) 1979-01-23 1979-01-23 Integrated circuit

Country Status (1)

Country Link
JP (1) JPS5599650A (en)

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS6370321A (en) * 1986-09-12 1988-03-30 Yokogawa Electric Corp Microprocessor
WO2002088913A1 (en) * 2001-04-27 2002-11-07 International Business Machines Corporation Method and apparatus for controlling processor operation speed

Cited By (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS6370321A (en) * 1986-09-12 1988-03-30 Yokogawa Electric Corp Microprocessor
WO2002088913A1 (en) * 2001-04-27 2002-11-07 International Business Machines Corporation Method and apparatus for controlling processor operation speed
GB2393294A (en) * 2001-04-27 2004-03-24 Ibm Method and apparatus for controlling processor operation speed
GB2393294B (en) * 2001-04-27 2005-04-06 Ibm Method and apparatus for controlling operation speed of processor
US7137017B2 (en) 2001-04-27 2006-11-14 International Business Machines Corporation Method and apparatus for controlling processor operation speed

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