JPS5769934A - Clock synchronizing system - Google Patents
Clock synchronizing systemInfo
- Publication number
- JPS5769934A JPS5769934A JP55146497A JP14649780A JPS5769934A JP S5769934 A JPS5769934 A JP S5769934A JP 55146497 A JP55146497 A JP 55146497A JP 14649780 A JP14649780 A JP 14649780A JP S5769934 A JPS5769934 A JP S5769934A
- Authority
- JP
- Japan
- Prior art keywords
- output
- clock
- gate
- pulse
- synchronize
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 230000015572 biosynthetic process Effects 0.000 abstract 1
- 230000001360 synchronised effect Effects 0.000 abstract 1
Classifications
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03L—AUTOMATIC CONTROL, STARTING, SYNCHRONISATION OR STABILISATION OF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES
- H03L7/00—Automatic control of frequency or phase; Synchronisation
Landscapes
- Stabilization Of Oscillater, Synchronisation, Frequency Synthesizers (AREA)
- Detection And Prevention Of Errors In Transmission (AREA)
- Time-Division Multiplex Systems (AREA)
Abstract
PURPOSE:To synchronize the clock of each system by providing a centralized gate which outputs an output taking a clock stop signal of each system as an input, with a clock generating circuit of each system constituting a multiplex system. CONSTITUTION:An oscillator 1 produces high-frequency output pulses functioning as the base of synchronizing clock formation. The output pulse of the oscillator1 is switched at a switch circuit 2 to form a synchronizing clock pulse. This synchronized clock pulse is counted for a prescribed number at a correction counter 3, and a count-up output is inputted to a centralized gate 4 via the switch circuit 2. Similar inputs from other systems II, III are given to the gate 4, and after stopping the clock output of the system I with the output of the correction counter 3, the stopping is released with the output of the gate 4, allowing to synchronize the clocks of the systems I, II, III.
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP55146497A JPS5769934A (en) | 1980-10-20 | 1980-10-20 | Clock synchronizing system |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP55146497A JPS5769934A (en) | 1980-10-20 | 1980-10-20 | Clock synchronizing system |
Publications (1)
Publication Number | Publication Date |
---|---|
JPS5769934A true JPS5769934A (en) | 1982-04-30 |
Family
ID=15408953
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP55146497A Pending JPS5769934A (en) | 1980-10-20 | 1980-10-20 | Clock synchronizing system |
Country Status (1)
Country | Link |
---|---|
JP (1) | JPS5769934A (en) |
Cited By (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS6332679U (en) * | 1986-08-12 | 1988-03-02 |
-
1980
- 1980-10-20 JP JP55146497A patent/JPS5769934A/en active Pending
Cited By (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS6332679U (en) * | 1986-08-12 | 1988-03-02 | ||
JPH0545944Y2 (en) * | 1986-08-12 | 1993-11-30 |
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