JPH0545944Y2 - - Google Patents

Description

[Detailed Description of the Invention] Industrial Application Field The present invention relates to an earthquake resistance test device equipped with a multi-waveform generation circuit that generates repetitive waveform signals necessary to independently operate a plurality of actuators.

BACKGROUND ART In seismic testing of structures, a plurality of actuators are used, each of which generates a load with a different waveform, thereby applying a load closer to the waveform actually applied to the structure. Therefore, each actuator operates and generates a load in accordance with an operation waveform supplied from a waveform generating circuit provided for each actuator.

Each actuator generates a load with a different operating waveform, but they are not independent waveforms that are unrelated to each other, but if the operating waveform is a repeating waveform, the waveforms of each actuator are different. The phase relationship between them is set to always be a constant relationship. For example, if the operating waveform of one actuator reaches its maximum value and the operating waveform of another actuator approaches a falling point, the relationship between these two must always be kept constant. It means that there is. Therefore, in the past, the time required for one cycle of the operating waveform was set to be equal to each other, and the operation of the waveform generation circuit was started at the same time as the test was started.

Problems that the invention aims to solve Load tests, etc. are performed using the above method, but as the test progresses, a shift begins to occur in the two relationships described above, that is, the phase relationship between the two waveforms. Eventually, the discrepancy will be such that it will interfere with the exam. This is because the time required for one cycle differs slightly between each waveform, and this minute difference is gradually accumulated. This slight difference in the time required for one cycle is mainly caused by rounding errors in calculations performed by the multi-waveform generator when setting different operating waveforms. , are the kinds of differences that are difficult to eliminate.

The present invention has been devised to solve the above problems, and its object is to provide an earthquake resistance testing device equipped with a multi-waveform generating circuit that does not cause the phase shift of the output waveforms even when the waveform generating circuits generate different waveforms and are used for long-term testing.

Means for Solving the Problems The seismic testing device equipped with the multi-waveform generation circuit according to the present invention has a total of n circuits that individually generate repetitive waveform signals, and when one cycle of the repetitive waveform is completed. A waveform generation circuit that outputs an end signal that provides timing, and a pair of each waveform generation circuit, and a total of n circuits that generate a start signal that provides timing for outputting a signal of a repetitive waveform, and are paired. The present invention is characterized in that it includes a synchronization circuit that outputs a start signal to the paired waveform generation circuit when all of the end signals introduced from other waveform generation circuits other than the waveform generation circuit are completed.

Effect: By starting to generate their own waveforms at the end of at least one cycle of all other waveform generation circuits, minute differences in the time required for each one cycle are absorbed as waiting time, and the difference is Do not accumulate.

Embodiment FIG. 2 is a schematic diagram showing a structure to which an embodiment of the present invention is applied. For example, a structure 51 made of iron or the like has four parts connected to an actuator 52.
The load generated by the actuator 52 is used to perform seismic strength tests and the like. At this time, the actuator 52 generates loads according to different waveforms, and the waveforms are repeating waveforms set to have the same period. The repetitive waveform is provided as a waveform output 23 from a multi-waveform generator, the details of which will be explained later.

FIG. 1 is a block diagram showing the electrical configuration of an embodiment of the present invention. The start signal 22a that causes the waveform generation circuit 12a to start generating a waveform is, for example,
Comprised of AND circuits, etc., termination signals 21b to 2 from all other waveform generation circuits 12b to 12d
The signal 1d is outputted by the synchronizing circuit 11a to which the signal 1d is input.

Similarly, each of the waveform generation circuits 12b to 12d receives the termination signal 21 of the other waveform generation circuit 12.
The start signals 22b to 22d from the synchronous circuits 11b to 11d to which the synchronous circuits 11b to 11d are connected are connected. The waveform generation circuit 12 sends out a waveform output 23 that determines the load waveform of the actuator 52 shown in FIG.

FIG. 3 is a timing chart showing the timing of main signals. Referring to FIG. 3, the operation of the seismic testing apparatus equipped with the multi-waveform generating circuit of the present invention will be described below. The waveform outputs 23 from the waveform generation circuit 12 are set so that the time t4 required for one cycle is the same, but due to rounding errors in calculations performed at the time of setting, etc., the time between each waveform output 23 may vary. There is a slight difference t5 (in Figure 3, the slight difference t5 is enlarged compared to the actual machine to make the timing easier to understand). Therefore, the time t1 at which one cycle of the waveform output 23 ends varies, and the end signal 2
1 are sent out at different timings.

When the waveform generation circuit 12a finishes generating a waveform for one cycle, t1, the input signal 3 to the synchronization circuit 11a is
Since only the H level indicating the end appears in the three end signals 21b to 21d, the H level indicating the start does not appear in the start signal 22a, and the waveform generating circuit 12a enters a standby state. At time t2, all of the end signals 21b to 21d are H indicating the end.
Since the level appears, an H level 81 is output as the start signal 22a, and the waveform generating circuit 12a starts generating one cycle of the waveform 82.

The above operation is performed by other waveform generation circuits 12b to 12d.
The same applies to the synchronous circuits 11b to 11d.
Since the only difference is the combination of end signals 21 inputted to the terminals, a description of the operation thereof will be omitted.

FIG. 4 is a block diagram showing the electrical configuration of another embodiment of the present invention.

The four end signals 21 output from the four waveform generation circuits 12 are input to a synchronization circuit 11e consisting of an AND circuit, etc., and the start signal 22 is output from the synchronization circuit 11e.
e is sent to four waveform generating circuits 12. The waveform outputs 23 are guided to respective actuators 52 (FIG. 2).

When one cycle of waveform generation is completed, the next cycle starts with the start signal 22e from the synchronization circuit 11e.
The generation of the waveform is waited until a signal indicating the start appears. When all of the end signals 21 from the four waveform generation circuits 12 appear indicating the end,
That is, when the waveform generation circuit 12 that takes the longest time for one cycle finishes generating one cycle of waveform, the synchronization circuit 11e outputs a signal indicating the start to the start signal 22. When the signal appears, the waveform generating circuit 12 starts generating a waveform for the next cycle.

Note that the present invention is not limited to the above-mentioned embodiments, and can be applied to cases where two, three, or five or more waveform generation circuits 12 are provided.

Effects of the invention The present invention absorbs minute differences in the time required for one cycle of the waveform generation circuits as waiting time and prevents accumulation of differences, so it can be used even when conducting long tests. , the phase of the output waveform does not shift. Therefore, unlike the conventional method, there is no fear that the test results will be affected by the phase shift of the output waveform, and the reliability of the device is increased.

[Brief explanation of the drawing]

Fig. 1 is a block diagram showing the electrical configuration of an embodiment of the present invention, Fig. 2 is a schematic diagram showing a structure to which an embodiment of the invention is applied, and Fig. 3 shows the timing of main signals. The timing chart shown in FIG. 4 is a block diagram showing the electrical configuration of another embodiment of the present invention. 11...Synchronization circuit, 12...Waveform generation circuit, 2
1... End signal, 22... Start signal, 23... Waveform output.

Claims (1)

[Scope of utility model registration request] In a seismic test equipment equipped with a multi-waveform generation circuit that generates each repetitive waveform signal necessary to independently operate a total of n actuators, a total of n actuators that individually generate repetitive waveform signals.
A waveform generation circuit that outputs a termination signal that indicates the timing at which one cycle of the repetitive waveform has ended, and a start signal that is paired with each waveform generation circuit and that provides the timing for outputting the signal of the repetitive waveform. A total of n circuits that generate
The present invention is characterized by comprising a synchronization circuit that outputs the start signal to the paired waveform generating circuit when all of the end signals introduced from other waveform generating circuits other than the paired waveform generating circuit are completed. Seismic test equipment equipped with a multi-waveform generation circuit.