JPS62297766A - Measuring instrument for logic integrated circuit - Google Patents

Abstract

PURPOSE:To prevent plural DUTs (correcting circuit element to be measured) from malfunctioning owing to wiring capacity by supplying an input signal which is restored accurately by using a latch signal right before the input terminal of a DUT to the input terminal of each DUT. CONSTITUTION:A clock generating device 1 is connected to the input terminal D of s shift register 3 through a frequency divider 2. The output CKphi of the device 1 is supplied to the shift pulse input terminal SP of the register 3 to obtain shift pulses. The register 3 shifts a signal to the terminal D with a signal to the terminal SP and outputs the signal. Output terminals Sphi and S1-Sn are selected with a switch 4 and the signal of the selected terminal is supplied as a latch pulse CKD to CK terminals of FFs Fphi and Fe-Fn. Input signals Aphi and Al-An from a signal source to D terminals of the FFs Fphi and FlnFn are latched with pulses CKD and outputted from output terminals Qo and Ql-Qn as output signals AXphi and Qn. Consequently, the signals which are waveform-shaped right before the input terminals of the DUTs, which are then prevented from malfunctioning.

Description

[Detailed description of the invention] 3. Detailed description of the invention Industrial applications The present invention relates to a measuring device for logic integrated circuits.

2. Description of the Related Art Conventionally, in a clock-synchronous logic integrated circuit measuring device having multiple input terminals, a signal is transmitted from a signal source to a device under test (hereinafter referred to as DUT) via a coaxial line or the like. An input signal having a pulse pattern is sent out in a time-accurate manner to the integrated circuit device under test (hereinafter referred to as DUT).
Performs necessary processing such as level conversion immediately before the input terminal of
This was used as an input signal to the DUT.

However, with this method, a time delay occurs in the signal depending on the distance of the signal line from the signal source to the DUT, and a time difference occurs in the signals between the multiple input terminals of the DUT, causing the DUT to not operate as expected. A problem occurs.

In other words, when measuring a clock-synchronous logic integrated circuit, if you try to measure multiple DUTs at the same time, the pattern signal at the receiving end will have a considerable waveform distortion compared to the pattern signal at the sending end. This causes a time difference in the logic signals between multiple input terminals of the DUT, resulting in multiple DUT
The operation differs between UTs. The situation,
This will be explained using FIGS. 4 to 6.

FIG. 4 is a diagram showing the connection state of each signal to the DUT, and FIG. 5 is a time chart in a normal case. CKφ is the DUT clock, CO2C1, C2 are the DU clock
It shows the operation timing inside T. It reads an input instruction at timing CO, decodes the instruction at timing C1, and outputs the result at timing C2. AO~
A3 is an input signal and provides an input command to OUT via four input terminals. BO to B2 are output signals, which are respectively output from the three output terminals of the DUT.

In this example, if input signals AO and A3 are both H, output signal BO becomes H, and input signals A1. If both A2 are H, the output signal BO is high and the output signal B1 is high.
This shows that the value becomes H. That is, input signals AO, A3
When both are H, CO2 which is the DUT internal timing
The DUT takes in the input command at timing , the DUT decodes the input command at timing 2 of DUT internal timing C1, and sets the output signal BO to H at timing 12 of H of DUT internal timing C2 immediately after that. Similarly, when input signals Al and A2 are both H, the DUT takes in the input command at timing Cφ5, and the DUT internal timing C
At timing 5 of 1, the DUT decodes the input command, and immediately after that, at timing 5 of H at internal timing C2, the output signal BO is turned off and Bl is set to H.

Problems to be Solved by the Invention By the way, if you try to operate multiple DUTs at a certain distance from a signal source at the same time via a coaxial line, etc.
Due to the wiring capacitance of coaxial lines, etc., waveform streaks occur, resulting in malfunctions. The situation is shown in FIG. In FIG. 6, the waveforms of the input signals AO to A3 are distorted due to the wiring capacitance. Therefore, although the input signals AO and A3 are originally H, the input signal A3 is actually
It accepts only the H of the input signals AO to A3 and mistakenly interprets it as a command to set the output signal B2 to H, resulting in an operation completely different from that shown in FIG. The timing of the import does not match and malfunctions.

In this way, conventional logic integrated circuit measurement equipment
Multiple DUTs can be connected depending on the length of the signal line, that is, the wiring capacity.
Each of them moves differently, which makes it difficult to measure.

The present invention solves the above-mentioned conventional problems, and
An object of the present invention is to provide a logic integrated circuit measuring device that can reliably prevent a UT from malfunctioning due to wiring capacitance.

Means for Solving the Problems In order to achieve this object, the present invention sends out a latch signal with an arbitrary delay time with respect to the clock of the DUT in parallel with the input signal. The input signal is accurately restored using the latch signal immediately before the terminal, and the restored signal is applied to the input terminal of each DUT.

Effect With this configuration, even if the waveform is distorted due to the wiring capacitance of the coaxial line, the signal whose waveform has been shaped just before the input terminal of the DUT is applied to the input terminal of the DUT.
It is possible to reliably prevent the UT from malfunctioning.

Embodiment FIGS. 1 to 3 show an embodiment of the present invention,
FIG. 1 is a block diagram, FIG. 2 is a timing chart of the operation shown in FIG. 1, and FIG. 3 is a diagram showing the connection state of the DUT at that time. In FIG. 1, reference numeral 1 denotes a clock generator that generates a clock called CKO, which is connected to the input terminal of a shift register 3 through a 1/n divider 2. On the other hand, shift pulse input terminal S of shift register 3
The output CKO of the clock generating device 1 is directly applied to P as a shift pulse. The shift register 3 transfers the signal applied to the input terminal to the shift pulse input terminal SP.
is shifted by the signal given to and output to output terminals 5o-8n. The output terminals SO to Sn are arbitrarily selected by the switch 4, and the signal of the selected terminal is the latch pulse C.
It is applied as KD to the CK terminals of flip-flops FO to Fn. The input signal AO-6=~An from a signal source (not shown) applied to the D terminal of the flip-flop FO-Fn is latched by the latch pulse CKD, and the output signal AxO-Axn is output from the output terminal QO-Qn. Output as .

In FIG. 2, the frequency division ratio of the frequency divider is set to 2 (n=2), and the latch pulse CKD is set to 1 of the output terminal SL of the shift register 3 (clock CKO from the clock generator l).
This figure illustrates the case where the delay by one cycle is selected.

As is clear from FIG. 2, the waveform distortion of the input signal AO-A3 is latched at the timing of the latch pulse CKD with a delay of CK(7) 1/2 period relative to the input signal AO-A31:1m, and the waveform is reshaped. Flip Flop FO
It is taken out from the output of ~Fn as A x O - A x n. These output signals AxO-Axn are applied to the input terminals of the DUT as shown in FIG. Therefore, the instruction capture timing is 2 times the DUT internal timing CO.
Although it will be delayed from 3 to 3, all subsequent operations are DU
Since it operates with a delay of one cycle of the internal timing CO, no malfunction will occur.

That is, the H command of the input signals Axe and Ax3 to the DUT is as follows:
It is taken in at timing 3 of the DUT internal timing CO, and outputted as an H output signal BO of the DUT at timing 3 of H of the internal timing C2 immediately thereafter. Similarly, the H command of the input signals Axl and Ax2 to the DUT is
DU is captured at timing 6 of internal timing CO, and immediately after that at timing 6 of H of internal timing C2.
The output signal BO of T is set to L, and the output signal B1 is set to H. That is,
In the case of FIG. 2, compared to the case of FIG. 5, the operation is the same except that the internal timing CO is delayed by one cycle, indicating that malfunctions can be prevented.

In the embodiment, the clock generator 1, frequency divider 2, and shift register 3 constitute means for outputting a latch signal.

Effects of the Invention As described above, in the present invention, a latch signal with an arbitrary delay time is sent out in parallel with the input signal with respect to the DUT clock, and these signals are used to improve (restore) the accuracy of the input signal. , to the input of each DUT, it is possible to correct waveform distortion due to wiring capacitance and eliminate DUT malfunctions.

[Brief explanation of the drawing]

Fig. 1 is a block diagram of a logic integrated circuit measuring device according to an embodiment of the present invention, Fig. 2 is a timing chart of each part of Fig. 1, and Fig. 3 is a DUT in the embodiment of Fig. 1.
FIG. 4 is a diagram showing the wiring state of a conventional DUT, and FIG. 5 is a diagram showing the wiring state of a conventional DUT. FIG. 6 is a conventional timing chart of each part. 1... Clock generator, 2... Frequency divider, 3... Shift register, 4... Switch, Fφ~Fn... Flip-flop, DUT
......Integrated circuit element to be measured. CKφ・・・・・・
Clock, CK...Clock frequency division signal, Aφ
~A3...Input signal, Axφ~Ax3...
...Flip-flop output signal (DUT input signal)
, Bφ~B2... Output signal, Aφ~An...
...Input signal, D...Input of shift register and flip-flop, SP...Shift pulse input terminal, Sφ~Sn...Output terminal of shift register, CKD. ...Latch pulse, QO-Qn
・・・・・・Output terminal of flip 70 tube, AXφ~A
xn...Flip-flop output signal (DUT
input signal), n... Frequency division ratio. Name of agent Patent attorney Toshio Nakao One idiot lO- C to F-m-Glock C bar-Grog's servant cy5~(:'2-DtJT operation timing ゛Fig. 2 β2 C bar-Clog AXf-AX3 -m-human power No. 01 B door ~ B2---1 Ka Sugino Figure 3 Figure 5 B? Figure 6

Claims (1)

[Claims] a signal source that sends out a plurality of input signals to be supplied to a plurality of input terminals of a clock-synchronous logic integrated circuit under test; and means for outputting a latch signal delayed by a predetermined time with respect to the clock of the logic integrated circuit under test. and means for latching the plurality of input signals with the latch signal, shaping the waveforms of the plurality of input signals, and applying the waveforms to the input terminals of the logic integrated circuit under test.