JP2994689B2 - Peak detector - Google Patents

Description

The present invention relates to a peak detector used for, for example, a spectrum analyzer.

[Prior Art] FIG. 5 shows the structure of a conventional peak detection circuit. 10 in the figure
Is the peak detection circuit, 20 is the sample and hold circuit, 30 is the AD
3 shows a converter. As is well known, the peak detecting circuit 10 includes an operational amplifier 1, a buffer amplifier 2, a peak hold diode 3 connected between the stages of the operational amplifier 1 and the buffer amplifier 2, a charging capacitor 4, and a reset switch 5. The output voltage of the buffer amplifier 2 is fed back to the inverting input terminal of the operational amplifier 1 by the feedback circuit 6 so that the inverting input terminal of the operational amplifier 1 is held at the peak detection voltage. The structure is such that the input signal taken in thereafter does not pass through the output side of the operational amplifier 1 unless it exceeds this peak value.

A sample-and-hold circuit 20 is connected to the output terminal of the buffer amplifier 2, and the hold voltage sampled and held by the sample-and-hold circuit 20 is applied to, for example, an AD converter 30, and the AD converter 30 converts the hold voltage into a digital signal.

This series of peak detection circuit 10 and sample hold circuit
20, the AD converter 30 operates in accordance with a predetermined order in synchronization with the clock PC shown in FIG. 6A.

That is, in the first half of each cycle T ₁ , T _2, ... Of the clock PC, the reset switch 5 provided in the sample and hold circuit 20 is turned on by the reset pulse PR, and the peak detection voltage Vp ( FIG. 6D) is reset. When the signal SP (FIG. 6C) is input to the input terminal after the reset, the charging capacitor 4 is charged with the peak detection voltage Vp corresponding to the peak value.

This peak detection voltage Vp is taken into the sample and hold circuit 20 at the timing of the clock PC in the next cycle. Sixth
Figure T _H represents a period in which the sample and hold circuit 20 is holding the voltage, AD converter 30 in this period completes the ID conversion operation. In this way, the period of the clock PC T ₁ , T ₂ …
Each time, peak detection, sample hold, and AD conversion operation are executed.

[Problems to be Solved by the Invention] In the peak detection circuit 10, if a large capacitance value of the charging capacitor 4 is adopted, it takes a long time to charge the battery, so that the peak value of a pulse having a narrow pulse width cannot be accurately obtained.

If the capacitance value of the charging capacitor 4 is small, the peak value of the input signal SP having a narrow pulse width can be accurately detected.

However, if the capacitance value of the charging capacitor 4 is too small, the holding time of the voltage becomes too short, so that the correct peak voltage cannot be transmitted to the sample and hold circuit 20.

Further, the illustrated conventional peak detection circuit has a drawback that the peak value cannot be detected even when the input signal SP is present in a state where the reset switch 5 is on, that is, during the reset period in which the reset pulse PR is present.

SUMMARY OF THE INVENTION It is an object of the present invention to provide a peak detection circuit which can accurately detect the peak value of a pulse having a narrow pulse width, has a long retention time for a peak detection voltage, and can detect the peak value of an input signal even in a reset state. It is something to offer.

[Means for Solving the Problems] In claim 1 of the present invention, the output of the first operational amplifier is supplied to the first charging capacitor through a peak holding diode, and the peak hold voltage charged in the first charging capacitor is calculated. Output as an output voltage and the first
The peak hold voltage charged in the charging capacitor is
The feedback is made to the inverting input terminal of the operational amplifier, the peak value of the input voltage given to the non-inverting input terminal is held in the first charging capacitor, and the peak value of the input voltage is supplied to the first charging capacitor by the first reset switch connected in parallel with the first charging capacitor. A low-speed response type peak detection circuit configured to reset the charged peak hold voltage; and an output of the second operational amplifier is supplied to a second charge capacitor having a smaller capacitance value than the first charge capacitor through a peak hold diode. The peak hold voltage charged in the second charging capacitor is fed back to the inverting input terminal of the second operational amplifier, and the peak value of the input voltage applied to the non-inverting input terminal of the second operational amplifier is held in the second charging capacitor. , A second reset switch connected in parallel to the second charging capacitor, Of the structure that resets the peak hold voltage charged to the battery
A high-speed response type peak detection circuit, and a third operational amplifier having an output of a third operational amplifier having a capacitance smaller than the first charging capacitor through a peak hold diode.
The peak hold voltage applied to the charging capacitor and charged in the third charging capacitor is fed back to the inverting input terminal of the third operational amplifier, and the peak value of the input voltage applied to the non-inverting input terminal of the third operational amplifier is calculated. The third charge capacitor holds the third charge capacitor and the third charge capacitor connected in parallel to the third charge capacitor.
A second fast response type peak detection circuit configured to reset the peak hold voltage charged in the third charge capacitor by a reset switch; a second operational amplifier and a second operation amplifier constituting the first and second fast response type peak detection circuits; An input terminal for supplying an input signal whose peak value is to be detected to both of the non-inverting input terminals of the three operational amplifiers, and output from the second and third charging capacitors of the first and second fast response type peak detection circuits. A selection switch for alternately selecting a peak hold voltage to be applied to a non-inverting input terminal of a first operational amplifier constituting a low-speed response type peak detection circuit; an operation of controlling the selection switch; Alternately selecting the peak hold voltage of the response type peak detection circuit and the second fast response type peak detection circuit,
In synchronization with the operation input to the low-speed response type peak detection circuit,
A flip-flop for performing an operation of alternately controlling the second reset switch or the third reset switch of the first fast response type peak detection circuit or the second fast response type peak detection circuit in which the selection switch is in a non-selection state to a reset state; Is proposed.

According to the second aspect of the present invention, the output of the first operational amplifier is supplied to the first charging capacitor through a peak holding diode, and the peak hold voltage charged in the first charging capacitor is fed back to the inverting input terminal of the first operational amplifier. And
The peak value of the input voltage applied to the non-inverting input terminal is
A low-speed response type peak detection circuit configured to hold the charge capacitor, a first reset switch for resetting the peak hold voltage held by the first charge capacitor at a predetermined timing, and an output of the second operational amplifier for peak hold. The peak hold voltage charged to the second charging capacitor having a smaller capacitance value than the first charging capacitor is fed back to the inverting input terminal of the second operational amplifier via the diode, and the peak hold voltage charged in the second charging capacitor is fed back to the inverting input terminal of the second operational amplifier. A high-speed response type peak detection circuit having a structure in which a peak value of an input voltage applied to a non-inverting input terminal is held by a second charging capacitor and the peak hold voltage is output to a low-speed response type peak detection circuit; It is connected in parallel with the peak hold diode that constitutes the peak detection circuit. It proposes a peak detector configured to hold voltage of high-speed response type peak detection circuit by the reset switch different timings by a second reset switch for resetting.

In any of the first and second aspects of the present invention, the high-speed response type peak detection circuit is arranged at the preceding stage, so that even if a pulse having a narrow pulse width is input, the peak voltage can be accurately detected by the high-speed response type peak detection circuit. Can be captured.

Moreover, in the first aspect of the present invention, the first high-speed response type peak detection circuit is connected in parallel with two first and second high-speed response type peak detection circuits, and the first and second high-speed response type peak detection circuits are alternately arranged. Even if an input signal is input at any timing because of operation, one of the high-speed response type peak detection circuits always captures the peak value and can transmit the peak voltage to the next-stage low-speed response type peak detection circuit. .

Furthermore, in the second aspect of the present invention, the high-speed response type peak detection circuit provided in the preceding stage of the low-speed response type peak detection circuit has a reset switch connected in parallel with the peak hold diode. Even if a peak signal is input to the circuit, the peak signal can be transmitted to the low-speed response type peak detection circuit through the reset switch, and the low-speed response type peak detection circuit can hold the peak voltage.

FIG. 1 shows an embodiment of the present invention. In this embodiment, first and second low-speed response type peak detection circuits
The high-speed response type peak detection circuits 10A and 10B are connected in parallel, and the first and second high-speed response type peak detection circuits 10A and 10B are configured to alternately perform a reset operation. 2 shows a case where the other high-speed response type peak detection circuit is configured to operate as a means for transmitting the input signal to the subsequent low-speed response type peak detection circuit even if an input signal exists.

The first and second high-speed response type peak detection circuits 10A and 10B and the low-speed response type peak detection circuit 10C are each composed of an operational amplifier 1, a buffer amplifier 2, a diode 3, a charging capacitor 4, and a reset, as described with reference to FIG. Switch 5, feedback circuit 6
Composed of

In the present invention, the non-inverting input terminals of the operational amplifiers 1 constituting the first and second fast response type peak detection circuits 10A and 10B are commonly connected, and the same input signal is supplied to the two operational amplifiers 1.

At the same time, a flip-flop 40 is provided, a sample-and-hold command signal HOLD to be supplied to, for example, the sample-and-hold circuit 20 is provided to the flip-flop 40, and the flip-flop 40 is inverted at the rising timing of the sample-and-hold command signal HOLD. Square wave CC and DD shown in
Get. The square waves CC and DD are applied to the reset switches 5 of the first and second fast response type peak detection circuits 10A and 10B and the selection switches 11A and 11B provided on the output side of each of the fast response type peak detection circuits 10A and 10B. Reset switch 5 provided in the first and second fast response type peak detection circuits 10A and 10B.
Are turned on and off alternately to control the first and second high-speed response type peak detection circuits 10A and 10B alternately to an operation state and a reset state, and to detect the high-speed response type peak detection in the operation state in synchronization with this. Selection switch 11A provided on the output side of the circuit
Or, control so that 11B is turned on.

That is, in this example, the rectangular wave CC is connected to the selection switch 11A and the reset switch 5 of the second fast response type peak detection circuit 10B.
And a rectangular wave DD is applied to the selection switch 11B and the reset switch 5 of the second fast response type peak detection circuit 10A.

As shown in the period T ₁ According to this configuration,
When the rectangular wave CC is in the L logic state and the rectangular wave DD is in the H logic state, the reset switch 5 of the first high-speed response type peak detection circuit 10A is turned on to be in the reset state, and the second high-speed response type peak detection circuit 10B is reset. The switch 5 is turned off and brought into an operating state.

Therefore, at this time, the selection switch 11A is controlled to be off because the rectangular wave CC has the L logic, and the selection switch 11B is controlled to be on. In Therefore the period T ₁ second fast-response peak detecting circuit 10B detects the peak voltage of the input signal, and transmits the slow response type peak detection circuit 10C of this peak detection voltage through the selection switch 11B.

In the rectangular wave CC is logic H, as shown in the period T _2, a rectangular wave
The first fast response type peak detection circuit when DD is L logic
The reset switch 5 of 10A is controlled to be turned off, and the reset switch 5 of the second fast response type peak detection circuit 10B is controlled to be turned on. Therefore, in the period T ₂ the first high-speed response type peak detection circuit 10A is the operating state, the second high-speed response type peak detection circuit 10B is a reset state, slow response type peak detection selection switch 11A is ON control The peak detection voltage of the first fast response type peak detection circuit 10A is transmitted to the circuit 10C.

Reset switch 5 of the slow response type peak detection circuit 10C
Is supplied with a reset pulse PR shown in FIG. 2C. The reset pulse PR discharges the peak detection voltage charged in the charging capacitor 4 during the period of H logic, and after the reset period ends, the low-speed response type peak detection circuit 10C is the first in the previous stage
Alternatively, the peak detection voltage of either one of the second high-speed response type peak detection circuits 10A and 10B is fetched. The peak detection voltage captured by the low-speed response type peak detection circuit 10C is sent to the sample and hold circuit 20 at the subsequent stage.

Thus, in the embodiment shown in FIG.
Since the high-speed response type peak detection circuits 10A and 10B are alternately operated, the input signal can be captured without leaking even instantaneously. In addition, since the peak voltage is detected by the first and second fast response type peak detection circuits 10A and 10B, the peak voltage can be accurately detected even with a pulse having a narrow pulse width.

In addition, the first and second fast response type peak detection circuits 10A
And the peak detection voltage detected by 10B is immediately taken into the slow response type peak detection circuit 10C. Therefore, even if the peak detection voltages of the first and second fast response type peak detection circuits 10A and 10B leak due to the shortage of the capacity of the charging capacitor 4, the voltage holding time of the low speed response type peak detection circuit 10C is long, so that the sample hold is performed. The detected peak voltage is transmitted to the circuit 20 as it is. Therefore, a peak detection voltage without error can be obtained.

"Modified Embodiment" FIG. 3 shows an embodiment of the peak detector proposed in claim 2 of the present invention. In this example, a slow response type peak detection circuit
This shows a case where one high-speed response type peak detection circuit 10D is arranged on the front stage side of 10C. The high-speed response type peak detection circuit 10D shows a configuration in which the reset switch 5 is connected in parallel to the peak hold diode 3.

By connecting the reset switch 5 in parallel to the peak hold diode 3 in this way, the backflow preventing action by the peak hold diode 3 is lost when the reset switch 5 is turned on.
The charging voltage of the charging capacitor 4 is absorbed by the operational amplifier 1 when the output potential of the operational amplifier 1 is low. That is, the voltage of the charging capacitor 4 moves following the output voltage of the operational amplifier 1. Therefore, if the input signal is in a non-signal state, the output voltage of the operational amplifier 1 is 0. Reset to zero.

When a signal is input during the reset period, the output voltage of the operational amplifier 1 changes in the same manner as the input signal. Therefore, the input signal is transmitted to the low-speed response type peak detection circuit 10C and is taken into the low-speed response type peak detection circuit 10C. .

This will be described with reference to FIG. Reset pulse pulse PR _a shown in FIG. 4 A to give the slow response type peak detection circuit 10C, a pulse PR _b shown in B shows a reset pulse applied to the high-speed response type peak detection circuit 10D.

In the reset state a reset pulse PR _b Fast Response type peak detection circuit 10D is in the logic H when the input signal SP as shown in FIG. 4 C is input, the output voltage VO of the high-speed response type peak detection circuit 10D is As shown in FIG. 4D, it changes in the same manner as the input signal SP.

By inputting the output voltage VO of the high-speed response type peak detection circuit 10D to the low-speed response type peak detection circuit 10C, the peak value of the input signal SP becomes a certain voltage even if it is not accurately taken in as shown in FIG. 4E. Up to VV can be captured.

[Effects of the Invention] As described above, according to the present invention, even when the high-speed response type peak detection circuit is in a reset state, the input signal is taken in directly or by another high-speed response type peak detection circuit and provided indirectly at the subsequent stage. Is transmitted to the low-speed response type peak detection circuit. Therefore, the input signal can be taken without dulling.

On the other hand, the first and second fast response type peak detection circuits 10A, 10B or 10D are arranged at the preceding stage, and the input signal S is input by the first and second fast response type peak detection circuits 10A, 10B and 10D.
Since the configuration is such that the peak of P is detected, even if the pulse width of the input signal SP is narrow, the peak voltage of that pulse can be accurately captured.

Further, the first and second fast response type peak detection circuits 10A,
As shown in FIG. 10B or the high-speed response type peak detection circuit 10D, a low-speed response type peak detection circuit is provided at the subsequent stage as shown in FIG.
The peak detection voltage captured by 10A, 10B or 10D may be captured by the low-speed response type peak detection circuit 10C, so that even if the capture operation is slightly delayed, the peak detection voltage does not include an error. Therefore, the peak value of the input signal can be accurately taken.

[Brief description of the drawings]

FIG. 1 is a connection diagram showing one embodiment of the present invention, FIG. 2 is a waveform diagram for explaining the operation of FIG. 1, FIG. 3 is a connection diagram showing a modified embodiment of the present invention, FIG. 3 is a waveform diagram for explaining the operation of FIG. 3, FIG. 5 is a connection diagram for explaining the conventional technique, and FIG. 6 is a waveform diagram for explaining the operation. 1: Operational amplifier, 2: Buffer amplifier, 3: Diode, 4: Charge capacitor, 5: Reset switch, 6: Feedback circuit, 10:
Peak detection circuit, 10A: first high-speed response type peak detection circuit,
10B: 2nd fast response type peak detection circuit, 10D: fast response type peak detection circuit, 10C: low speed response type peak detection circuit, 20: sample hold circuit.

Claims (2)

(57) [Claims] A. An output of a first operational amplifier is supplied to a first charging capacitor through a diode for peak holding, and a peak holding voltage charged in the first charging capacitor is output as an output voltage. The peak hold voltage charged in one charging capacitor is equal to the first hold voltage.
A feedback is made to the inverting input terminal of the operational amplifier, the peak value of the input voltage applied to the non-inverting input terminal is held by the first charging capacitor, and the first reset switch connected in parallel with the first charging capacitor causes the first reset switch to be connected to the first charging capacitor. A low-speed response type peak detection circuit configured to reset the peak hold voltage charged in the charge capacitor; and B. the second charge having a smaller capacitance value than the first charge capacitor, wherein the output of the second operational amplifier passes through a peak hold diode. The peak hold voltage supplied to the capacitor and charged in the second charging capacitor is fed back to the inverting input terminal of the second operational amplifier, and the peak value of the input voltage supplied to the non-inverting input terminal of the second operational amplifier In the second charging capacitor, and a second reset switch connected in parallel to the second charging capacitor. C. a first high-speed response type peak detection circuit configured to reset the peak hold voltage charged in the second charge capacitor by a switch, and C. the output of the third operational amplifier passes through a diode for peak hold to the first charge capacitor. The peak hold voltage charged to the third charge capacitor having a smaller capacitance value is fed back to the inverting input terminal of the third operational amplifier, and is supplied to the non-inverting input terminal of the third operational amplifier. A peak value of the applied input voltage is held in the third charging capacitor, and the peak hold voltage charged in the third charging capacitor is reset by a third reset switch connected in parallel with the third charging capacitor. (2) a high-speed response type peak detection circuit, and D. the first high-speed response type peak detection circuit and the second An input terminal for supplying an input signal whose peak value is to be detected to both the non-inverting input terminals of the second operational amplifier and the third operational amplifier constituting the fast response type peak detection circuit; and E. the first fast response type peak detection. Circuit and the second fast-response type peak detection circuit, the second charging capacitor and the third
A selection switch for alternately selecting a peak hold voltage output from the charging capacitor and applying the peak hold voltage to a non-inverting input terminal of a first operational amplifier constituting the low-speed response type peak detection circuit; and F. an operation for controlling the selection switch And the selection switch alternately selects the peak hold voltage of the first high-speed response type peak detection circuit and the peak hold voltage of the second high-speed response type peak detection circuit, and synchronizes with the operation of inputting to the low-speed response type peak detection circuit. The first switch in which the selection switch is not selected.
A flip-flop for executing an operation of alternately controlling the second reset switch or the third reset switch of the high-speed response type peak detection circuit or the second high-speed response type peak detection circuit to the reset state. Detector. 2. An output of the first operational amplifier is supplied to a first charging capacitor through a diode for peak holding, and a peak hold voltage charged in the first charging capacitor is supplied to an inverting input terminal of the first operational amplifier. And the peak value of the input voltage given to the non-inverting input terminal is
B. a low-speed response type peak detection circuit configured to hold the charge capacitor; B. a first reset switch for resetting the peak hold voltage held by the first charge capacitor at a predetermined timing; C. output of the second operational amplifier Is supplied to a second charge capacitor having a smaller capacitance value than the first charge capacitor through a peak hold diode, and a peak hold voltage charged in the second charge capacitor is fed back to an inverting input terminal of the second operational amplifier. A high-speed response having a structure in which a peak value of an input voltage applied to a non-inverting input terminal of the second operational amplifier is held by the second charging capacitor, and the peak hold voltage is output to the low-speed response type peak detection circuit. D. A peak detection circuit, and D. a peak hold circuit that constitutes this high-speed response type peak detection circuit. It is connected in parallel with diode, peak detector, characterized by being configured by a second reset switch for resetting the hold voltage of the high-speed response type peak detection circuit at different timings with the first reset switch.