JP2630081B2 - Switched capacitor circuit - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a switched capacitor circuit, and more particularly, to a switched capacitor circuit which performs switching by an output control signal of a switched capacitor type comparator.

[0002]

2. Description of the Related Art A conventional switched capacitor circuit has an operational amplifier 1 as shown in FIG.
1, a switched capacitor type comparator 1 including switches 12 to 14 and a capacitance 15, a delay circuit 2,
It comprises a flip-flop 3, a control circuit 4, and a switch control circuit 5. Here, regarding the components of the switched capacitor type comparator 1, the switch 12 is a switch that is turned on at the timing of the clock signal 132, and the switches 13 and 14
Are switches that are turned on at the timing of the clock signal 133, respectively. The capacitor 15 is a capacitor for accumulating electric charges, and the operational amplifier 11 is
Has a function of determining whether the charge stored in the memory is positive or negative.

In FIG. 4, an input signal 130 and a reference signal 131 are supplied to a switched capacitor type comparator 1.
And to the switch circuit 5. In the switched capacitor type comparator 1, the magnitude relation between the input signal 130 and the reference signal 131 is determined, and the determined output signal is transmitted to the D-type flip-flop 3 via the delay circuit 2.
A signal synchronized with the clock signal 134 (inverted clock signal of the clock signal 132) input to the terminal and input to the C terminal of the D-type flip-flop 3 is output and input to the control circuit 4. The switch switching control signal 135 is output from the control circuit 4 and is input to the switch circuit 5.
The switch switching control signal 135 is output in a state where a delay of at least one clock or more occurs after the magnitude relationship between the input signal 130 and the reference signal 131 is determined in the nT time. That is, the time required for switching the switch in the switch circuit 5 is at least (n
+1) T time or later.

On the other hand, the level of the input signal 130 input to the switch circuit 5 is changed between time nT and time (n + 1) T, so that the output signal 136 of the switch circuit 5 is determined. The level changes continuously from the set time nT to the actually switched time (n + 1) T. FIG. 6 is a time chart showing the states of the clock signals 132 and 133, the input signal 130, the reference signal 131, and the output signal 136 in this case.
(A), (b), (c) and (d).

[0005]

In the conventional switched-capacitor circuit described above, the time required to determine the level of the input signal and the reference signal in the switched-capacitor-type comparator and the actual time required for the switch are determined. Since there is a delay time synchronized with the clock signal between the control time and the control time, as shown in FIG. 6C, the level of the input voltage changes during the delay time at the output of the switch circuit. To this extent, there is a disadvantage that a discontinuous portion is generated in terms of voltage, and there is a disadvantage that the symmetry at the rise and fall of the input signal is lost.

[0006]

SUMMARY OF THE INVENTION A switched capacitor circuit according to the present invention is arranged such that the input signal and the reference signal are supplied via first and second clock signals in response to input of a predetermined input signal and a reference signal. A switched-capacitor comparator that determines the magnitude of the level, a delay circuit that delays the output signal of the switched-capacitor comparator for a predetermined time and outputs the delayed signal, and inputs an output signal of the delay circuit to a D terminal. A D-type flip-flop that inputs an inverted clock signal of the first clock signal from a C terminal and outputs a signal synchronized with the inverted clock signal of the second clock signal from a Q terminal; A control circuit that receives an output signal and outputs a predetermined switch switching control signal; and a control circuit that receives the predetermined input signal and receives the first and second input signals. At a timing synchronized with the lock signal, a charge transfer type analog delay circuit that delays the input signal for a predetermined time and outputs the same, an output signal of the charge transfer type analog delay circuit, and the reference signal, and And a switch circuit for selecting and outputting one of them via a control signal.

[0007]

Next, embodiments of the present invention will be described with reference to the drawings.

FIG. 1 is a block diagram showing one embodiment of the present invention. As shown in FIG. 1, this embodiment includes a switched capacitor type comparator 1 including an operational amplifier 11, switches 12 to 14, and a capacitance 15, and a delay circuit 2.
, A D-type flip-flop 3, a control circuit 4, a switch circuit 5, and a charge transfer type analog delay circuit 6. Here, the components of the switched capacitor type comparator 1 are the same as in the case of the conventional example.
The switch 12 is a switch that is turned on at the timing of the clock signal 103, and the switches 13 and 14
Are switches that are turned on at the timing of the clock signal 104, respectively. The capacitor 15 is a capacitor for accumulating electric charges, and the operational amplifier 11 is
Has a function of determining whether the charge stored in the memory is positive or negative.

In FIG. 1, an input signal 101 is input to a switched capacitor type comparator 1 and a charge transfer type analog delay circuit 6. Also, the reference signal 102
Is input to the switched capacitor type comparator 1 and the switch circuit 5. In the switched capacitor type comparator 1, the magnitude relationship between the input signal 130 and the reference signal 131 is determined as in the case of the conventional example, and the determined output signal is passed through the delay circuit 2 to the D flip-flop 3. D-type flip-flop 3
A signal synchronized with the clock signal 105 (inverted clock signal of the clock signal 104) input to the C terminal is output and input to the control circuit 4. The switch switching control signal 106 is output from the control circuit 4 and input to the switch circuit 5.

On the other hand, in the charge transfer type analog delay circuit 6, the charge transfer to the input signal 101 is performed via the clock signals 103 and 104, and the charge transfer time t _T is longer than that of the switched capacitor type comparator 1.
, The control circuit 4 outputs the switch switching control signal 106 via the delay circuit 2, the D-type flip-flop 3 and the control circuit 4 from the time for determining the magnitude relationship between the input signal 101 and the reference signal 102. Time until the same time. The voltage level of the input signal 101 in the switched capacitor type comparator 1 during the level determination time appears as the output of the charge transfer type analog delay circuit 6 after the time t _T. FIGS. 5A, 5B, 5C, and 5D are time charts showing states of the clock signals 103 and 104, the input signal 101, the reference signal 102, and the output signal 107 in this case.
Is shown in Therefore, in this embodiment, the output signal 1
07, the discontinuous voltage level range is suppressed, and the apparent overshoot amount is reduced. Input signal 101
Is a waveform sampled and held at the timing of the clock signal 103 or 104, the effect of reducing the overshoot amount is further increased.

FIG. 2 shows an example in which the present invention is applied to a mute circuit. As shown in FIG. 2, this mute circuit includes a switched capacitor type comparator 1, a delay circuit 2, and a D-type flip-flop 3.
Are provided, and a control circuit 4, a charge transfer type analog delay circuit 6, a switch circuit 5, and an addition circuit 7 are provided as circuit elements common to the two circuit systems. ing.

In FIG. 2, an input signal 108 is commonly input to two switched capacitor type comparators 1 and a charge transfer type analog delay circuit 6. The reference signals 109 and 110 are individually input to the two switched capacitor comparators 1. In the switched capacitor type comparator 1 in each system, the input signal 108, the reference signal 109, and the input signal
The magnitude relationship between the reference signal 110 and the reference signal 110 is individually determined, and the determination output signal is input to the common control circuit 4 via the respective delay circuits 2 and D-type flip-flops 3. From the control circuit 4, switch switching control signals 116 and 117 are output and input to the switch circuit 5. The switch circuit 5 is formed of a pair of switches 16 and 17, and these switches are operated by being controlled by the switch switching control signals 116 and 117, respectively.

On the other hand, in the charge transfer type analog delay circuit 6, charge transfer to the input signal 108 is performed via the clock signals 112 and 113. The charge transfer time is the same as that of the above-described embodiment. In the switched capacitor type comparator 1, the input signal 108 and the reference signal 109 or the input signal 108 and the reference signal 11
The time from the time of judging the magnitude relation to 0 to the time from when the control circuit 4 outputs the switch switching control signal 116 or 117 via the delay circuit 2, the D-type flip-flop 3 and the control circuit 4 is the same as the time. I do. The input signal delayed in the charge transfer type analog delay circuit 6 is input to the switch 16 of the switch circuit 5, but the other switch 17 of the switch circuit 4 is connected to a reference voltage 111 (usually a ground potential). ing. By setting the switch circuit 5 to operate when the level of the input signal 108 is higher than the reference signal 109 and lower than the reference voltage 110, this circuit functions as a mute circuit. In this mute circuit, the input waveform is totally delayed by the charge transfer type analog delay circuit 6 in order to maintain the symmetry at the rise and fall of the input signal 108.

FIG. 3 shows an example in which the present invention is applied to a limiter circuit. As shown in FIG. 3, the present limiter circuit includes a switched capacitor type comparator 1, a delay circuit 2, and a D-type flip-flop 3.
Are provided, and a control circuit 4, a charge transfer type analog delay circuit 6, a switch circuit 5, and an addition circuit 7 are provided as circuit elements common to the two circuit systems. ing.

In FIG. 3, an input signal 119 is commonly input to two switched capacitor type comparators 1 and a charge transfer type analog delay circuit 6. Also, the high-level reference signal 120 and the low-level reference signal 1
21 are individually input to the two switched capacitor type comparators 1. In the switched capacitor type comparator 1 in each system, the magnitude relationship between the input signal 119 and the high-level reference signal 120 and the magnitude relationship between the input signal 119 and the low-level reference signal 121 are individually determined as in the case of the conventional example. The determination output signal is input to a common control circuit 4 via each delay circuit 2 and D-type flip-flop 3. From the control circuit 4, switch switching control signals 126, 127 and 128 are output and input to the switch circuit 5. The switch circuit 5 is formed by three sets of switches 18, 19 and 20, and these switches are connected to the switch switching control signal 12 described above, respectively.
6, 127 and 128 to operate.

On the other hand, in the charge transfer type analog delay circuit 6, charges are transferred to the input signal 119 via the clock signals 122 and 123. The charge transfer time is the same as that of the above-described embodiment. In the switched-capacitor comparator 1, the time for determining the magnitude relationship between the input signal 119 and the high-level reference signal 120 or the input signal 119 and the low-level reference signal 121 is determined by:
Delay circuit 2, D-type flip-flop 3, and control circuit 4
From the control circuit 4 via the switch switching control signal 12
It is set to be the same as the time until it is output as 6 or 127 or 128. The input signal delayed by the charge transfer type analog delay circuit 6 is input to the switch 19 of the switch circuit 5, and the other switches 18 and 20 of the switch circuit 4 are supplied to the high level reference signal 120 and the low level reference signal, respectively. Signal 121 is connected. In the switch circuit 5, depending on whether the level of the input signal 119 is higher than the high-level reference signal 109, lower than the low-level reference signal 110, or an intermediate level between the high-level reference signal and the low-level reference signal. In addition, a limiter circuit of a type in which whether to select an input signal, a high-level reference signal, or a low-level reference signal as an output signal is configured. In this limiter circuit, the charge transfer type analog delay circuit 6 delays the input signal 119 itself, thereby preventing ringing that occurs when the limiter is sensed.

[0017]

As described above, according to the present invention, a charge transfer type analog delay circuit is inserted between an input signal input to a switched capacitor type comparator and a switch circuit, so that the input signal can be appropriately processed. By applying a long delay time, a voltage value substantially the same as the voltage value at the time of determining the magnitude of the input signal and the reference signal in the switched capacitor type comparator can be input to the switch circuit. There is an effect that voltage discontinuity can be suppressed and unnecessary overshoot or ringing can be prevented.

[Brief description of the drawings]

FIG. 1 is a block diagram showing one embodiment of the present invention.

FIG. 2 is a block diagram showing a mute circuit as one application example of the embodiment.

FIG. 3 is a block diagram showing a limiter circuit as one application example of the embodiment.

FIG. 4 is a block diagram showing a conventional example.

FIG. 5 is a diagram showing operation waveforms in the present embodiment.

FIG. 6 is a diagram showing operation waveforms in a conventional example.

[Explanation of symbols]

 DESCRIPTION OF SYMBOLS 1 Switched capacitor type comparator 2 Delay circuit 3 D type flip-flop 4 Control circuit 5 Switch circuit 6 Charge transfer type analog delay circuit 7 Addition circuit 11 Operational amplifier 12-14, 16-20 Switch

Claims (1)

(57) [Claims] 1. A switched-capacitor-type comparator for determining the level of the input signal and the reference signal via first and second clock signals in response to input of a predetermined input signal and a reference signal. A delay circuit that delays the output signal of the switched capacitor type comparator by a predetermined time and outputs the delayed signal; and inputs an output signal of the delay circuit to a D terminal, and outputs an inverted clock signal of the first clock signal from a C terminal. A D-type flip-flop for inputting a signal synchronized with an inverted clock signal of the second clock signal from a Q terminal, and a predetermined switch switching control signal And a control circuit that outputs the input signal and the input signal at a timing synchronized with the first and second clock signals. A signal transfer type analog delay circuit for delaying a signal by a predetermined time, and an output signal of the charge transfer type analog delay circuit and the reference signal are input, and any one of them is input via the switch switching control signal. And a switch circuit for selecting and outputting.