JP2786320B2 - Sample hold circuit - Google Patents

Description

Description: BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a sample and hold circuit, and more particularly, to an A / D circuit.
The present invention relates to a sample and hold circuit suitable for use as an input circuit of a converter.

2. Description of the Related Art A sample-and-hold circuit is used in an A / D converter, and the sample-and-hold circuit shown in FIG. 3, for example, is known. This circuit includes sampling gate diodes 2, 3, 4, 5, sample voltage hold capacitance 6, output buffer circuit 7,
Sampling signal negative-phase input transistor 8, sampling signal positive-phase input transistor 9, sampling gate negative current source transistors 10, 11, sampling gate positive current distribution transistors 12, 13, 14, 15, sampling gate positive current source Transistor 16, output buffer circuit current source transistors 17, 18, sampling gate
A bootstrap pull-up diode 19 and a sampling gate bootstrap pull-down diode 20 are provided.The sampling gate positive current source control voltage V _GB1 is applied to the gate of the transistor 16, and the gate of the transistor 17 is connected to the gate of the transistor 17. Is applied with the current source control voltage V _GB2 for the output buffer circuit.

In the above circuit, a signal to be sampled as shown in FIG. 4A is input to a terminal 1, a sampling reverse phase signal as shown in FIG. A terminal 22 receives a sampling positive-phase signal as shown in FIG. 4C. Then, a sampled signal as shown in FIG. 4B is output from the terminal 23. Then, when the signal to be sampled a is input to the terminal 1 at time t ₀ , this signal is input to the junction between the diodes 2 and 3. At this time, since the ON signal is input to the transistor 8 and the OFF signal is input to the transistor 9, the diodes 2, 3
Are in reverse bias, and transmission of the sampled signal is blocked. Further, at this time, since the diodes 4 and 5 are both in a reverse bias state, no signal to be sampled is input to the capacitance 6.

Then, the transistor 8 is turned off at time t _1, when the transistor 9 is changed to ON, the diode 2, 3, 4, 5 are all turned on, the sampling signal capacitance 6
Is input to That is, when the diodes 2, 3, 4, 5 constituting the analog switch are turned on, charges are accumulated in the capacitance 6. This condition is continued to the time t ₂ until the sampling positive phase signal c and the sampling phase signal d is inverted with respect to each other. In FIG. 4 (B), ts indicates a settling time, and is a time from the start of the sampling period until the output signal sampled becomes equal to the input signal.
That is, the settling time ts is a time until the terminal voltage of the capacitance 6 holding one previous sampling state catches up with the input signal for the next sampling. Therefore, the accumulation of charges in the capacitance 6 is continued until a time longer than the settling time ts, that is, until time t2. Then at time t2, the diode 2, 3, 4, 5 are all turned off, the terminal voltage of the capacitance 6 remains holding the instantaneous voltage at time t ₂ of the sampling signal a. Then, the terminal voltage of the capacitance 6 is outputted from the terminal 23 as the output signal b sampled via the output buffer circuit 7. This state is continued until all the diodes 2, ₃ , 4, and 5 are turned on again at time t3.

However, in the conventional circuit, the electric charge accumulated in the capacitance 6 is discharged by the leak current of each element connected to the terminal of the capacitance 6 and the input current of the output buffer circuit 7. As a result, the terminal voltage of the capacitance 6 gradually decreases as shown in FIG. This change is called a droop (DROOP). This droop is not impossible to adjust when the sample-and-hold circuit is manufactured as a discrete component (discrete component).
When using multiple sample-and-hold circuits as the input circuit of the A / D converter, the variation in the droop value of each sample-and-hold circuit occurs due to the variation in the characteristics of the components that make up the circuit, but in order to absorb this variation, Adjustment of the droop value of each sample-and-hold circuit was impossible at all.

An object of the present invention is to provide a sample that can suppress variations in droop characteristics caused by variations in characteristics of components constituting a circuit such as discrete components when a plurality of sample and hold circuits are used as an input circuit of an A / D converter. An object of the present invention is to provide a hold circuit.

Means for Solving the Problems In order to achieve the above object, the present invention provides an analog switch that inputs a signal to be sampled, intermittently outputs the signal to be sampled, and a switching device that receives the sampling signal and switches the analog switch. A sample and hold circuit having control means, voltage holding means for holding an output voltage of an analog switch, and output buffer means for extracting and outputting the voltage held by the voltage holding means, wherein the voltage is held in parallel with the voltage holding means. A sample-and-hold circuit is characterized in that a charge-holding means is provided which is grounded in parallel with the holding means and directly stores the charge, and the capacitance of which is changed by a control signal.

According to the present invention, when a droop occurs when a signal to be sampled is sampled, if the capacity of the charge storage means is adjusted by the control signal, the output charge of the voltage holding means becomes equal to the capacity of the charge storage means. Since the voltage is accumulated, the output voltage of the voltage holding means is prevented from lowering.
Since the value of the droop can be adjusted, it is possible to reduce errors due to variations in individual droop values in the plurality of sample and hold circuits.

Embodiment FIG. 1 shows a configuration of a sample and hold circuit according to an embodiment of the present invention. In FIG. 1, the sample and hold circuit is a sampling gate diode.
2, 3, 4, 5, capacitance for holding sample voltage 6, output buffer circuit 7, negative input transistor 8 for sampling signal, positive input transistor 9 for sampling signal, transistors 10 and 11 for sampling gate negative current source, Sampling gate positive current distribution transistors 12, 13, 14, 1
5, sampling gate transistor for positive current source 16,
It has current source transistors 17 and 18 for the output buffer circuit, pull-up diode 19 for sampling gate bootstrap, and pull-down diode 21 for sampling gate bootstrap, and stores electric charge in parallel with capacitance 6 Coupling capacitor constituting means
24 and a variable capacity diode 25 are provided. A terminal 1 receives a sampled signal, a terminal 21 receives a sampling reverse phase signal, a terminal 22 receives a sampling normal phase signal, and a terminal 23 outputs a sampled signal. Has become. In addition, the terminal
A signal for diode bias control is input to 26.

The coupling capacitor 24 and the variable capacitance diode 25 are respectively connected in series, and the variable capacitance diode 25 is directly grounded. Further, a diode bias control signal e is supplied to those connection points. And diode
Reference numeral 25 indicates that the junction capacitance (capacitance) C changes according to the value of the control signal e. As shown in FIG. 2, the junction capacitance C changes with characteristics as shown in the following equation (1).

C = A (Φ−V) ^1/2 (1) where A is a proportionality constant, Φ is a bias-specific value, and V is a bias voltage. In FIG. 2, what is shown as a 1/2 power characteristic indicates a theoretical value based on the above equation (1), and what is shown as the present invention shows the characteristic of the diode 25 as one embodiment. . The change in the capacitance C does not need to completely match the theoretical characteristic, and it is required that the capacitance C changes in accordance with the bias voltage V substantially in accordance with the theoretical characteristic within a practical range. FIG. 2 shows actual characteristics when the present invention is realized.

In the above configuration, when a signal to be sampled is input to the terminal 1, the signal to be sampled
The diodes 2, 3,
Only when all of the signals 4 and 5 are turned on, the signal is input to the capacitance 6. This state continues until the diodes 2, 3, 4, and 5 are turned off. After that, the output voltage of the analog switch is held in the capacitance 6 and the coupling capacitor 24 is turned off.
And is held by the diode 25. At this time, when the value of the droop is large, by changing the level of the control signal e, it is possible to prevent the junction capacitance C of the diode 25 from changing and increasing the value of the droop. By performing such an adjustment, the level of the droop can be suppressed to a low level without changing the value of the control signal e when the signal to be sampled is next input. Furthermore, since the junction capacitance C can be adjusted by changing the value of the control signal e applied to the terminal 26, the value of the droop can be adjusted from the outside even when the sample-and-hold circuit is integrated, For example, in an apparatus using a plurality of integrated sample-and-hold circuits, the droop value is made the same to reduce an error due to droop, or a standard for the droop value of an integrated circuit having a sample-and-hold circuit is given a range. This can contribute to cost reduction.

According to the present invention, as is apparent from the above embodiment, the charge storage means is provided in parallel with the voltage holding means, and the output voltage of the analog switch is held by the voltage holding means and the charge storage means.
Since the capacity of the charge storage means can be adjusted, it is possible to suppress variations in individual droop values in a plurality of sample and hold circuits, to reduce errors due to variations in droop values, and to improve the characteristics of sampling signals. Can be improved.

[Brief description of the drawings]

FIG. 1 is a circuit diagram showing a sample and hold circuit according to one embodiment of the present invention, FIG. 2 is a characteristic diagram of a variable capacitance diode, FIG. 3 is a circuit diagram of a conventional example, and FIG. FIG. 4 is a waveform diagram for explaining. 2,3,4,5 …… Sampling gate diode, 6…
... Capacitance for holding sample voltage, 7 ... Output buffer circuit, 8 ... Sampling signal negative-phase input transistor, 9 ... Sampling signal positive-phase input transistor, 1
0,11… Sampling gate negative current source transistor, 12, 13, 14, 15… Sampling gate positive current distribution transistor, 16… Sampling gate positive current source transistor, 24… For coupling Condenser, 25 ... Diode for variable capacitance.

Claims (1)

(57) [Claims] An analog switch for inputting a signal to be sampled and outputting the signal to be sampled intermittently;
A sample-and-hold circuit having switching control means for switching an analog switch in response to a sampling signal, voltage holding means for holding an output voltage of the analog switch, and output buffer means for taking out and outputting the voltage held by the voltage holding means , A charge storage means, which is grounded in parallel and directly with the voltage holding means, stores charge and changes the capacitance in response to a control signal, and changes the control signal from outside to provide the voltage holding means. A sample-and-hold circuit for adjusting a droop value while suppressing a decrease in the output voltage of the sample-hold circuit.