CA2073958C - Phase shift sample-and-hold circuit for determining the mean amplitude for periodic pulses - Google Patents
Phase shift sample-and-hold circuit for determining the mean amplitude for periodic pulsesInfo
- Publication number
- CA2073958C CA2073958C CA 2073958 CA2073958A CA2073958C CA 2073958 C CA2073958 C CA 2073958C CA 2073958 CA2073958 CA 2073958 CA 2073958 A CA2073958 A CA 2073958A CA 2073958 C CA2073958 C CA 2073958C
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- CA
- Canada
- Prior art keywords
- pulse
- phase shifted
- voltage
- sample
- sampling
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Fee Related
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Classifications
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C27/00—Electric analogue stores, e.g. for storing instantaneous values
- G11C27/02—Sample-and-hold arrangements
- G11C27/024—Sample-and-hold arrangements using a capacitive memory element
- G11C27/026—Sample-and-hold arrangements using a capacitive memory element associated with an amplifier
Abstract
A phase shift sample-and-hold circuit which determines the mean amplitude of a selected portion of a periodic pulse is provided. A periodic input pulse issuccessively phase shifted by two time delays in order to provide a first phase shifted pulse and a second phase shifted pulse. The first phase shifted pulse isbuffered and applied to an integrating sample-and-hold circuit which integrates the buffered pulse during a sampling interval. The required sampling interval isgenerated by the combined operation of a comparator means and a logic means which provide a sampling command during the time interval when both the original input pulse and the second phase shifted pulse exceed a predetermined DC threshold voltage and intersect with each other. The integrated mean amplitude of the sampled portion of the first phase shifted pulse is held until the sampling of the next cycle.
Description
A PIIASE SHIFT SAMPLE-AND-HOLD CIRCUIT FOR
DETERMINING TEIE MEAN AMPLITUDE OF PERIODIC PULSES
TECHNICAL ~IELD
s This invention relates to ele~ vllic sample-and-hold circuits, and more particularly to a phase shift sample-and-hold circuit which determin~s the mean amplitude of a selected portion of a periodic pulse.
BACEGROUND OF THE INVENTION
It is common in electronic sample-and-hold systems to sample a portion of an input signal and to hold the voltage of the sampled portion until it has beenprocç~eed When it is nr~ S..y to measure the mean ~mplit~lde of a specific 15 portion of a periodic pulse, as in the case of hiom.o,~lical or col."lll.ications clc~llol~ics, most prior art ~7y~ltllls employ a digital sampling technique or an analogue integr~t1on technique.
The digital sampling technique involves the sequential sampling of many small increments of an input pulse and the conversion of these inclc;.,.enl~ to digital data for the p~se of further computer procç~ing. Prior art systems employing this technique operate in conjunction with incrçm.o,nt~l sample-and-hold circuits which require the use of complicated periph.o,ral circuits for the control of the ~mpling interval as shown in U.S. Patent No. 5,081,372, issued to M.J.M.
Pelgrom on Jan. 14, 1992.
The analogue integration technique involves the integration of an input pulse when it exceeds a fixed threshold voltage as shown in C~n~ n Patent No.
958,119, issued to H. Gahwiler on Nov. 19, 1974. Prior art ::iy~lelllS employing this technique will integrate any portion of the input pulse which exceeds the threshold voltage. Consequently, the system may integrate undesired portions of the input pulse such as the pulse over~h- ot, ringing, rise time, or fall time. Errors may result in the n.ea~ ent of mean pulse amplitudes because the system sampling interval has not been limited to the applop.iate portions of the input pulse.
SUMMARY OF TEIE INVENTION
Accordingly, an object of the present invention is to provide an improved sample-and-hold circuit which measures the mean amplitude of a selected portion of a periodic pulse.
Another object of the present invention is to provide a method of phase shift sampling which does not require the use of complicated peripheral circuits or coml.uler procç~ing.
The above and other objects of the present invention are achieved by providing a phase shift sample-and-hold circuit which successively phase shifts a 10 periodic input pulse prior to integrated sampling in order to generate an a~lopllate sampling time interval. A periodic input pulse is phase shifted by a first time delay in order to provide a first phase shifted pulse. The first phase shifted pulse is further phase shifted by a second time delay in order to provide a second phase shifted pulse. The first phase shifted pulse is buffered by a buffer amplifer and 15 applied to the input of an integrating sample-and-hold circuit which consists of a switch, an integrator, and a sample-and-hold amplif er.
An appropliate sampling interval is generated by the combined operation of a first co...~ .t~r, a second col,l~aldlor, and an AND gate. The first comr~rat~r provides a logic high output signal only when the original input pulse exceeds a20 pre-letetmin~d DC threshold voltage while the second comr~rat. r provides a logic high output signal only when the second phase shifted pulse exceeds the same predetelmined DC threshold voltage. The AND gate output provides a logic high sampling signal only when the output signals from the both the first c..~ tor and the second c~ tor are ~imlllt~neously logic high. The resulting sampling 25 interval, which occurs during the peak amplitude period of the first phase shifted pulse, starts when the leading edge of the second phase shifted pulse rises above the DC threshold voltage, and stops when the trailing edge of the original input pulse falls below the DC threshold voltage. During the s~m~ling interval, when the ANDgate is providing a logic high ~mrling signal to the switch of the integrating 30 sample-and-hold circuit, the first phase shifted pulse is integrated. The mean amplitude of the ~m~letl portion of the first phase shifted pulse is held at the output of the integrating saml,le-and-hold circuit until the ~mrlin~ of the next cycle.These and other objects, features and advantages of the present invention will be more clearly lm~kr~tood from the following clet~ile.l desw;plion taken in 35 conjunction with the accol~lyillg drawings.
.
CA 020739~8 1998-09-10 BRIEF DESCRIPTION OF THE DRAWINGS
In drawings which illustrate embotlim~nt~ of the invention:
FIG. 1 illustrates in partial schematic form a sample-and-hold circuit S embodying the present invention;
FIG. 2 illustrates in partial sç~em~tiC form another embodiment of the present invention; and FIG. 3 illustrates in grarhir~l form the voltage signals associated with the circuits of FIGS. 1 and 2.
DETAILED DESCRIPTION OF TIIE INVENTION
Shown in FIG. 1 is a sample-and-hold circuit embodying the present invention wherein input pulse voltage Vi is coupled to t~rmin~l 10. Input pulse 15 voltage Vi is sllcceccively phase shifted by time delays 12 and 13. Time delay 12 provides a phase shifted pulse voltage Va which lags input pulse voltage Vi by time interval tl. Time delay 13 provides a phase shifted pulse voltage Vb which lags pulse voltage Va by time interval t2, and input pulse voltage Vi by the sum of time intervals tl and t2.
Threshold voltage Vt is coupled to termin~l 11 for the pul~ose of comparison to pulse voltages Vi and Vb. The threshold c~ Ip~ on is n~cecc~ry in order to prevent the undesired sampling of low level input noise. Threshold voltage Vt is a ~l~dete~ ed DC voltage which may range anywhere in m~gnitllrle from zero to the peak amplitude of input pulse voltage Vi. C'nmr~ratnr 14 has a first input 25 coupled to pulse voltage Vb, and a second input coupled to threshold voltage Vt.
C~ p~ tnt 15 has a first input coupled to input pulse voltage Vi, and a second input coupled to threshold voltage Vt. Comr~rfltnr~ 14 and 15 provide logic highoutput signals to dual-input AND gate 16 only when pulse voltages Vb and Vi exceed threshold voltage Vt, respectively. AND gate 16 provides a logic high 30 sampling voltage Vs to switch 31 only when the output signals from cunlpdldtors 14 and 15 are ~imtllt~n~ously logic high and inter~ect As switch 31 is made conductive when s~mrlin~ voltage Vs is at a logic high level, it follows that switch 31 cnn-lllct~ only when pulse voltages Vb and Vi exceed threshold voltage Vt andint~rsect with each other. More specifically, switch 31 starts cnn~ cting when the 35 leading edge of pulse voltage Vb rises above threshold voltage Vt, and stops CA 020739~8 1998-09-10 cnn~ tin~ when the trailing edge of input pulse voltage Vi falls below thresholdvoltage Vt.
Pulse voltage Va is buffered by buffer amplifier 20 and then coupled to the input of integrating sample-and-hold circuit 30 which consists of switch 31, S integrator 32, and sample-and-hold ampli~ler 33. Pulse voltage Va is buffered prior to integrated sampling in order to prevent undesired signal loading and distortion.
The phase relationship between pulse voltage Va and sampling voltage Vs, which is established by time delays 12 and 13, ~leterminPs the portion of pulse voltage Va to be sampled by integrating sample-and-hold circuit 30.
When switch 31 is made conductive by sampling voltage Vs, buffered pulse voltage Va is coupled to integrator 32. Integrator 32 provides an output voltage to sample-and-hold ~m~lifi~r 33 which equals the mean amplitude of the sampled portion of buffered pulse voltage Va. Sample-and-hold amplifier 33 holds the mean amplitude of buffered pulse voltage Va during the time that switch 31 is made nonconductive by sampling voltage Vs. DC output voltage Vo, which is provided by the output of sample-and-hold ~mplifier 33 and is coupled to terminal 34, equals the mean amplitude of the sampled portion of buffered pulse voltage Va. As pulsevoltage Va is simply a phase shifted adaption of input pulse Vi, output voltage Vo also represents the mean amplitude of a selected portion of input voltage Vi.
Shown in FIG. 2 is an exemplary embo-liment of the present invention, which is a modification of the sample-and-hold circuit shown in FIG. 1. For convenience of illustration, elements which are common with the circuit of FIG. 1 are id~nti~-~lly numbered in FIG. 2. For p~ oses of illustration only, the circuit shown in FIG. 2 is configured for the mean amplitude measurement of positive periodic pulses. Itshould be clear that the present invention may be configured for the meaxu~ ent of po~ilive or negative pulses.
~lme delays 12 and 13 are leple3ented in FIG. 2 as unity-gain buffer ampliiiers. Time intervals tl and t2 are provided by the respective propagation delays of the buffer ~mrlifier~ used as time delays 12 and 13. It should be clear that other electronic devices such as ~loJJ~ ble digital delay circuits may be used to provide the required time delays in the present invention. Ct~mr~r~tor 14 has a noninverting input coupled to pulse voltage Vb, and an inverting input coupled to threshold voltage Vt. C~ .Al,.t~- 15 has a noninverting input coupled to input pulse voltage Vi, and an inverting input coupled to threshold voltage Vt.
Cu~ tors 14 and 15 work in conjunction with AND gate 16 to provide s~mrling A
CA 020739~8 1998-09-10 _,.
s voltage Vs in exactly the same manner as the sample-and-hold circuit of FIG. 1.
For the mea~ c;llt of negative periodic pulses, the connections to the invertingand noninverting inputs of c~ p~l~tnre 14 and 15 are reversed.
Threshold voltage Vt, which is a pre-l~t~rmin~d DC voltage ranging anywhere 5 in mApnitllde from zero to the peak amplitude of input pulse voltage Vi, may be provided by means other than a fixed DC voltage source. The circuit of FIG. 2 may further colllL,.~e a peak hold means for providing a floating DC threshold voltage which equals a predçtçrmin~d fraction of the peak voltage of periodic input pulse Vi thus minimi~in~ interference from low level noise over a wide range of input 10 pulse Am~lihldçs It should be clear that any means may be used to provide the required DC threshold voltage in the present invention.
Pulse voltage Va is buffered by buffer amplifier 20 prior to sampling by integrated sample-and-hold circuit 30. Buffer amplifier 20 consists of operational amplifier 23, and resistors R21 and R22. Rç-cietnre-R2l and R22 are made equal in 15 value so that opçrAti~nAlAm~lifier23 provides an inverting unity-gain output to int.ogrAting sample-and-hold circuit 30.
It should be clear that the int~grAtor means and the sample-and-hold amplifier means required by the present invention may be combined into the operation of a single integrating s~le-and-hold amplifier circuit c .Illp, i~ an operational amplifier c~ ed to both an integration feedhAck loop and a sample-and-hold feerlhack loop. Integrating sample-and-hold circuit 30, which c~mhin~s the operations of integration and sampling into one process, consists of operationalamplifier 33, switch 31,cApAr-itorC37, and resistors R32,R35, and R36. Switch 31, which may be implementçd with any type of switching device, becomes conductive when eAm~ling voltage Vs is logic high. During the sampling interval when switch 31is made conductive, buffered pulse voltage Va is sampled and int~gtAtç~l by integrating sample-and-hold circuit 30 which provides output voltage Vo to terminAl 34.
Output voltage Vo, which equals the mean amplitude of the sampled portion of buffered pulse voltage Va, is held by capAeit.rC37 during the time interval when switch 31is made nonconductive by sAmrlin~ voltage Vs. R~-cictnrcR35 and R36 are made equal in value so that operAtionAl amplifier 33 provides an inverting DC
voltage gain of unity. The values of capacitor C37, resistor R32, and resistor R36 d~t~ ç the amount of waveform int~gration provided by operational amplifier 33. The inclusion of resistor R32 in the circuit allows the amount of waveform CA 020739~8 1998-09-10 integration provided by operational amplifier 33 to be adjusted independently of the DC voltage gain. The product of the respective inverting voltage gains of bufferamplifier 20 and integrating sample-and-hold circuit 30 provides the relationship between pulse voltage Va and output voltage Vo, which may be expressed 5 mathem~tic~lly as:
Vo = Va ~ [-R22/R21] ~ [-R36/R35] ~ [1 ~ -t/(R36 2R32)c37]
where t equals the sampling time interval of pulse voltage Va in seconds.
In order to provide adequate integration of the sampled portion of pulse voltage Va, the time constant (R36 + 2R32)C37 must be at least five times greater than the 10 sampling time interval provided by sampling voltage Vs. It should be clear that the present invention may further colllpl~e an instrllment~tion means, such as an analogue or digital voltmeter, for visually displaying Vo.
Shown in FIG. 3 are graphs of the voltage signals associated with the circuits of FIGS. 1 and 2. For pul~oses of illustration only, input pulse voltage Vi is 15 lepl~ellled as a positive pulse waveform. Input pulse voltage Vi is successively phase shifted by time intervals tl and t2. Phase shifted pulse voltage Va lags input pulse voltage Vi by time interval tl. Phase shifted pulse voltage Vb lags pulse voltage Va by time interval t2, and input pulse voltage Vi by the sum of time intervals t 1 and t2. Pulse voltages Vi and Vb are c~nlp~ed to DC threshold voltage 20 Vt. When pulse voltages Vi and Vb exceed threshold voltage Vt and intersect with each other, sampling voltage Vs becomes logic high in value. Pulse voltage Va isintegrated and sampled during time intervals ta, tc, and te, when sampling voltage Vs is logic high in value. More specifically, the integration and sampling of pulse voltage Va starts when the leading edge of pulse voltage Vb rises above threshold 25 voltage Vt, and stops when the trailing edge of input pulse voltage Vi falls below threshold voltage Vt. It should be clear that the phase relationship between pulse voltages Vi, Va, and Vb, which is established by time intervals tl and t2, dete~nines the portion of pulse voltage Va to be s~mple.l During time intervals tb and td, when sampling voltage Vs is zero, output voltage Vo is held at a DC level 30 which equals the mean ~mplit~lde of the sampled portion of pulse voltage Va.
In summary, the phase shift sample-and-hold circuit of the present invention ~letermines the mean amplitude of any selected portion of a periodic pulse without the use of complicated peripher~l circuits or computer pi~ce~ g. The adjustment of two sllece~ive time delays selects the portion of the periodic pulse amplitude to 35 be s~mpl~.l by the present invention, and prevents the sampling of undesired A
CA 020739~8 1998-09-10 portions of the periodic pulse such as the pulse overshoot, rin~ing, rise time, and fall time. Hence, the determination of mean pulse amplitudes may be made accurately according to the teaching of the present invention.
While there is shown and described preferred embo~liment~ of the present S invention, it is to be distinctly ~lntl.or~tood by those skilled in the art that the present invention is not limited thereto but may be otherwise variously embodied and practiced within the scope of the following claims.
DETERMINING TEIE MEAN AMPLITUDE OF PERIODIC PULSES
TECHNICAL ~IELD
s This invention relates to ele~ vllic sample-and-hold circuits, and more particularly to a phase shift sample-and-hold circuit which determin~s the mean amplitude of a selected portion of a periodic pulse.
BACEGROUND OF THE INVENTION
It is common in electronic sample-and-hold systems to sample a portion of an input signal and to hold the voltage of the sampled portion until it has beenprocç~eed When it is nr~ S..y to measure the mean ~mplit~lde of a specific 15 portion of a periodic pulse, as in the case of hiom.o,~lical or col."lll.ications clc~llol~ics, most prior art ~7y~ltllls employ a digital sampling technique or an analogue integr~t1on technique.
The digital sampling technique involves the sequential sampling of many small increments of an input pulse and the conversion of these inclc;.,.enl~ to digital data for the p~se of further computer procç~ing. Prior art systems employing this technique operate in conjunction with incrçm.o,nt~l sample-and-hold circuits which require the use of complicated periph.o,ral circuits for the control of the ~mpling interval as shown in U.S. Patent No. 5,081,372, issued to M.J.M.
Pelgrom on Jan. 14, 1992.
The analogue integration technique involves the integration of an input pulse when it exceeds a fixed threshold voltage as shown in C~n~ n Patent No.
958,119, issued to H. Gahwiler on Nov. 19, 1974. Prior art ::iy~lelllS employing this technique will integrate any portion of the input pulse which exceeds the threshold voltage. Consequently, the system may integrate undesired portions of the input pulse such as the pulse over~h- ot, ringing, rise time, or fall time. Errors may result in the n.ea~ ent of mean pulse amplitudes because the system sampling interval has not been limited to the applop.iate portions of the input pulse.
SUMMARY OF TEIE INVENTION
Accordingly, an object of the present invention is to provide an improved sample-and-hold circuit which measures the mean amplitude of a selected portion of a periodic pulse.
Another object of the present invention is to provide a method of phase shift sampling which does not require the use of complicated peripheral circuits or coml.uler procç~ing.
The above and other objects of the present invention are achieved by providing a phase shift sample-and-hold circuit which successively phase shifts a 10 periodic input pulse prior to integrated sampling in order to generate an a~lopllate sampling time interval. A periodic input pulse is phase shifted by a first time delay in order to provide a first phase shifted pulse. The first phase shifted pulse is further phase shifted by a second time delay in order to provide a second phase shifted pulse. The first phase shifted pulse is buffered by a buffer amplifer and 15 applied to the input of an integrating sample-and-hold circuit which consists of a switch, an integrator, and a sample-and-hold amplif er.
An appropliate sampling interval is generated by the combined operation of a first co...~ .t~r, a second col,l~aldlor, and an AND gate. The first comr~rat~r provides a logic high output signal only when the original input pulse exceeds a20 pre-letetmin~d DC threshold voltage while the second comr~rat. r provides a logic high output signal only when the second phase shifted pulse exceeds the same predetelmined DC threshold voltage. The AND gate output provides a logic high sampling signal only when the output signals from the both the first c..~ tor and the second c~ tor are ~imlllt~neously logic high. The resulting sampling 25 interval, which occurs during the peak amplitude period of the first phase shifted pulse, starts when the leading edge of the second phase shifted pulse rises above the DC threshold voltage, and stops when the trailing edge of the original input pulse falls below the DC threshold voltage. During the s~m~ling interval, when the ANDgate is providing a logic high ~mrling signal to the switch of the integrating 30 sample-and-hold circuit, the first phase shifted pulse is integrated. The mean amplitude of the ~m~letl portion of the first phase shifted pulse is held at the output of the integrating saml,le-and-hold circuit until the ~mrlin~ of the next cycle.These and other objects, features and advantages of the present invention will be more clearly lm~kr~tood from the following clet~ile.l desw;plion taken in 35 conjunction with the accol~lyillg drawings.
.
CA 020739~8 1998-09-10 BRIEF DESCRIPTION OF THE DRAWINGS
In drawings which illustrate embotlim~nt~ of the invention:
FIG. 1 illustrates in partial schematic form a sample-and-hold circuit S embodying the present invention;
FIG. 2 illustrates in partial sç~em~tiC form another embodiment of the present invention; and FIG. 3 illustrates in grarhir~l form the voltage signals associated with the circuits of FIGS. 1 and 2.
DETAILED DESCRIPTION OF TIIE INVENTION
Shown in FIG. 1 is a sample-and-hold circuit embodying the present invention wherein input pulse voltage Vi is coupled to t~rmin~l 10. Input pulse 15 voltage Vi is sllcceccively phase shifted by time delays 12 and 13. Time delay 12 provides a phase shifted pulse voltage Va which lags input pulse voltage Vi by time interval tl. Time delay 13 provides a phase shifted pulse voltage Vb which lags pulse voltage Va by time interval t2, and input pulse voltage Vi by the sum of time intervals tl and t2.
Threshold voltage Vt is coupled to termin~l 11 for the pul~ose of comparison to pulse voltages Vi and Vb. The threshold c~ Ip~ on is n~cecc~ry in order to prevent the undesired sampling of low level input noise. Threshold voltage Vt is a ~l~dete~ ed DC voltage which may range anywhere in m~gnitllrle from zero to the peak amplitude of input pulse voltage Vi. C'nmr~ratnr 14 has a first input 25 coupled to pulse voltage Vb, and a second input coupled to threshold voltage Vt.
C~ p~ tnt 15 has a first input coupled to input pulse voltage Vi, and a second input coupled to threshold voltage Vt. Comr~rfltnr~ 14 and 15 provide logic highoutput signals to dual-input AND gate 16 only when pulse voltages Vb and Vi exceed threshold voltage Vt, respectively. AND gate 16 provides a logic high 30 sampling voltage Vs to switch 31 only when the output signals from cunlpdldtors 14 and 15 are ~imtllt~n~ously logic high and inter~ect As switch 31 is made conductive when s~mrlin~ voltage Vs is at a logic high level, it follows that switch 31 cnn-lllct~ only when pulse voltages Vb and Vi exceed threshold voltage Vt andint~rsect with each other. More specifically, switch 31 starts cnn~ cting when the 35 leading edge of pulse voltage Vb rises above threshold voltage Vt, and stops CA 020739~8 1998-09-10 cnn~ tin~ when the trailing edge of input pulse voltage Vi falls below thresholdvoltage Vt.
Pulse voltage Va is buffered by buffer amplifier 20 and then coupled to the input of integrating sample-and-hold circuit 30 which consists of switch 31, S integrator 32, and sample-and-hold ampli~ler 33. Pulse voltage Va is buffered prior to integrated sampling in order to prevent undesired signal loading and distortion.
The phase relationship between pulse voltage Va and sampling voltage Vs, which is established by time delays 12 and 13, ~leterminPs the portion of pulse voltage Va to be sampled by integrating sample-and-hold circuit 30.
When switch 31 is made conductive by sampling voltage Vs, buffered pulse voltage Va is coupled to integrator 32. Integrator 32 provides an output voltage to sample-and-hold ~m~lifi~r 33 which equals the mean amplitude of the sampled portion of buffered pulse voltage Va. Sample-and-hold amplifier 33 holds the mean amplitude of buffered pulse voltage Va during the time that switch 31 is made nonconductive by sampling voltage Vs. DC output voltage Vo, which is provided by the output of sample-and-hold ~mplifier 33 and is coupled to terminal 34, equals the mean amplitude of the sampled portion of buffered pulse voltage Va. As pulsevoltage Va is simply a phase shifted adaption of input pulse Vi, output voltage Vo also represents the mean amplitude of a selected portion of input voltage Vi.
Shown in FIG. 2 is an exemplary embo-liment of the present invention, which is a modification of the sample-and-hold circuit shown in FIG. 1. For convenience of illustration, elements which are common with the circuit of FIG. 1 are id~nti~-~lly numbered in FIG. 2. For p~ oses of illustration only, the circuit shown in FIG. 2 is configured for the mean amplitude measurement of positive periodic pulses. Itshould be clear that the present invention may be configured for the meaxu~ ent of po~ilive or negative pulses.
~lme delays 12 and 13 are leple3ented in FIG. 2 as unity-gain buffer ampliiiers. Time intervals tl and t2 are provided by the respective propagation delays of the buffer ~mrlifier~ used as time delays 12 and 13. It should be clear that other electronic devices such as ~loJJ~ ble digital delay circuits may be used to provide the required time delays in the present invention. Ct~mr~r~tor 14 has a noninverting input coupled to pulse voltage Vb, and an inverting input coupled to threshold voltage Vt. C~ .Al,.t~- 15 has a noninverting input coupled to input pulse voltage Vi, and an inverting input coupled to threshold voltage Vt.
Cu~ tors 14 and 15 work in conjunction with AND gate 16 to provide s~mrling A
CA 020739~8 1998-09-10 _,.
s voltage Vs in exactly the same manner as the sample-and-hold circuit of FIG. 1.
For the mea~ c;llt of negative periodic pulses, the connections to the invertingand noninverting inputs of c~ p~l~tnre 14 and 15 are reversed.
Threshold voltage Vt, which is a pre-l~t~rmin~d DC voltage ranging anywhere 5 in mApnitllde from zero to the peak amplitude of input pulse voltage Vi, may be provided by means other than a fixed DC voltage source. The circuit of FIG. 2 may further colllL,.~e a peak hold means for providing a floating DC threshold voltage which equals a predçtçrmin~d fraction of the peak voltage of periodic input pulse Vi thus minimi~in~ interference from low level noise over a wide range of input 10 pulse Am~lihldçs It should be clear that any means may be used to provide the required DC threshold voltage in the present invention.
Pulse voltage Va is buffered by buffer amplifier 20 prior to sampling by integrated sample-and-hold circuit 30. Buffer amplifier 20 consists of operational amplifier 23, and resistors R21 and R22. Rç-cietnre-R2l and R22 are made equal in 15 value so that opçrAti~nAlAm~lifier23 provides an inverting unity-gain output to int.ogrAting sample-and-hold circuit 30.
It should be clear that the int~grAtor means and the sample-and-hold amplifier means required by the present invention may be combined into the operation of a single integrating s~le-and-hold amplifier circuit c .Illp, i~ an operational amplifier c~ ed to both an integration feedhAck loop and a sample-and-hold feerlhack loop. Integrating sample-and-hold circuit 30, which c~mhin~s the operations of integration and sampling into one process, consists of operationalamplifier 33, switch 31,cApAr-itorC37, and resistors R32,R35, and R36. Switch 31, which may be implementçd with any type of switching device, becomes conductive when eAm~ling voltage Vs is logic high. During the sampling interval when switch 31is made conductive, buffered pulse voltage Va is sampled and int~gtAtç~l by integrating sample-and-hold circuit 30 which provides output voltage Vo to terminAl 34.
Output voltage Vo, which equals the mean amplitude of the sampled portion of buffered pulse voltage Va, is held by capAeit.rC37 during the time interval when switch 31is made nonconductive by sAmrlin~ voltage Vs. R~-cictnrcR35 and R36 are made equal in value so that operAtionAl amplifier 33 provides an inverting DC
voltage gain of unity. The values of capacitor C37, resistor R32, and resistor R36 d~t~ ç the amount of waveform int~gration provided by operational amplifier 33. The inclusion of resistor R32 in the circuit allows the amount of waveform CA 020739~8 1998-09-10 integration provided by operational amplifier 33 to be adjusted independently of the DC voltage gain. The product of the respective inverting voltage gains of bufferamplifier 20 and integrating sample-and-hold circuit 30 provides the relationship between pulse voltage Va and output voltage Vo, which may be expressed 5 mathem~tic~lly as:
Vo = Va ~ [-R22/R21] ~ [-R36/R35] ~ [1 ~ -t/(R36 2R32)c37]
where t equals the sampling time interval of pulse voltage Va in seconds.
In order to provide adequate integration of the sampled portion of pulse voltage Va, the time constant (R36 + 2R32)C37 must be at least five times greater than the 10 sampling time interval provided by sampling voltage Vs. It should be clear that the present invention may further colllpl~e an instrllment~tion means, such as an analogue or digital voltmeter, for visually displaying Vo.
Shown in FIG. 3 are graphs of the voltage signals associated with the circuits of FIGS. 1 and 2. For pul~oses of illustration only, input pulse voltage Vi is 15 lepl~ellled as a positive pulse waveform. Input pulse voltage Vi is successively phase shifted by time intervals tl and t2. Phase shifted pulse voltage Va lags input pulse voltage Vi by time interval tl. Phase shifted pulse voltage Vb lags pulse voltage Va by time interval t2, and input pulse voltage Vi by the sum of time intervals t 1 and t2. Pulse voltages Vi and Vb are c~nlp~ed to DC threshold voltage 20 Vt. When pulse voltages Vi and Vb exceed threshold voltage Vt and intersect with each other, sampling voltage Vs becomes logic high in value. Pulse voltage Va isintegrated and sampled during time intervals ta, tc, and te, when sampling voltage Vs is logic high in value. More specifically, the integration and sampling of pulse voltage Va starts when the leading edge of pulse voltage Vb rises above threshold 25 voltage Vt, and stops when the trailing edge of input pulse voltage Vi falls below threshold voltage Vt. It should be clear that the phase relationship between pulse voltages Vi, Va, and Vb, which is established by time intervals tl and t2, dete~nines the portion of pulse voltage Va to be s~mple.l During time intervals tb and td, when sampling voltage Vs is zero, output voltage Vo is held at a DC level 30 which equals the mean ~mplit~lde of the sampled portion of pulse voltage Va.
In summary, the phase shift sample-and-hold circuit of the present invention ~letermines the mean amplitude of any selected portion of a periodic pulse without the use of complicated peripher~l circuits or computer pi~ce~ g. The adjustment of two sllece~ive time delays selects the portion of the periodic pulse amplitude to 35 be s~mpl~.l by the present invention, and prevents the sampling of undesired A
CA 020739~8 1998-09-10 portions of the periodic pulse such as the pulse overshoot, rin~ing, rise time, and fall time. Hence, the determination of mean pulse amplitudes may be made accurately according to the teaching of the present invention.
While there is shown and described preferred embo~liment~ of the present S invention, it is to be distinctly ~lntl.or~tood by those skilled in the art that the present invention is not limited thereto but may be otherwise variously embodied and practiced within the scope of the following claims.
Claims (5)
1. A phase shift sample-and-hold circuit which determines the mean amplitude of a selected portion of a periodic pulse, comprising:
a first time delay means for phase shifting a periodic input pulse in order to provide a first phase shifted pulse;
a second time delay means for further phase shifting the first phase shifted pulse in order to provide a second phase shifted pulse;
buffer amplifier means for buffering the first phase shifted pulse prior to integration and sampling;
integrator means for integrating the first phase shifted pulse during a specificsampling interval in order to provide an output voltage which equals the mean amplitude of a selected portion of the periodic input pulse;
sample-and-hold amplifier means for holding the output voltage of the integrator means until the phase shift sampling of the next cycle of the periodic input pulse;
a first comparator means for providing a logic high output signal only when the original input pulse exceeds a predetermined DC threshold voltage;
a second comparator means for providing a logic high output signal only when the second phase shifted pulse exceeds a predetermined DC threshold voltage;
AND gate logic means for providing a logic high sampling signal only when the output signals from both the first comparator and the second comparator are simultaneously logic high; and switching means for selectively applying the first phase shifted pulse to the integrator means only during the sampling interval when a logic high sampling signal is provided by the AND gate logic means.
a first time delay means for phase shifting a periodic input pulse in order to provide a first phase shifted pulse;
a second time delay means for further phase shifting the first phase shifted pulse in order to provide a second phase shifted pulse;
buffer amplifier means for buffering the first phase shifted pulse prior to integration and sampling;
integrator means for integrating the first phase shifted pulse during a specificsampling interval in order to provide an output voltage which equals the mean amplitude of a selected portion of the periodic input pulse;
sample-and-hold amplifier means for holding the output voltage of the integrator means until the phase shift sampling of the next cycle of the periodic input pulse;
a first comparator means for providing a logic high output signal only when the original input pulse exceeds a predetermined DC threshold voltage;
a second comparator means for providing a logic high output signal only when the second phase shifted pulse exceeds a predetermined DC threshold voltage;
AND gate logic means for providing a logic high sampling signal only when the output signals from both the first comparator and the second comparator are simultaneously logic high; and switching means for selectively applying the first phase shifted pulse to the integrator means only during the sampling interval when a logic high sampling signal is provided by the AND gate logic means.
2. The circuit of claim 1, wherein the first and second time delay means comprise a programmable digital delay circuit.
3. The circuit of claim 1, wherein the integrator means and the sample-and-hold amplifier means are combined into the operation of a single integrating sample-and-hold amplifier circuit comprising an operational amplifier connected to both an integration feedback loop and a sample-and-hold feedback loop.
4. The circuit of claim 1, further comprising a peak hold means for providing a floating DC threshold voltage which equals a predetermined fraction of the peak voltage of the periodic input pulse.
5. The circuit of claim 1, further comprising an instrumentation means for visually displaying the measured mean amplitude of the periodic input pulse.
Priority Applications (2)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CA 2073958 CA2073958C (en) | 1992-07-15 | 1992-07-15 | Phase shift sample-and-hold circuit for determining the mean amplitude for periodic pulses |
| GB9226194A GB2269066B (en) | 1992-07-15 | 1992-12-16 | A phase shift sample-and-hold circuit for determining the mean amplitude of periodic pulses |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CA 2073958 CA2073958C (en) | 1992-07-15 | 1992-07-15 | Phase shift sample-and-hold circuit for determining the mean amplitude for periodic pulses |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CA2073958A1 CA2073958A1 (en) | 1994-01-16 |
| CA2073958C true CA2073958C (en) | 1999-03-23 |
Family
ID=4150161
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CA 2073958 Expired - Fee Related CA2073958C (en) | 1992-07-15 | 1992-07-15 | Phase shift sample-and-hold circuit for determining the mean amplitude for periodic pulses |
Country Status (2)
| Country | Link |
|---|---|
| CA (1) | CA2073958C (en) |
| GB (1) | GB2269066B (en) |
Families Citing this family (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| DE102018104547A1 (en) * | 2018-02-28 | 2019-08-29 | Universität Paderborn | Integrating and holding circuit |
-
1992
- 1992-07-15 CA CA 2073958 patent/CA2073958C/en not_active Expired - Fee Related
- 1992-12-16 GB GB9226194A patent/GB2269066B/en not_active Expired - Fee Related
Also Published As
| Publication number | Publication date |
|---|---|
| CA2073958A1 (en) | 1994-01-16 |
| GB9226194D0 (en) | 1993-02-10 |
| GB2269066A (en) | 1994-01-26 |
| GB2269066B (en) | 1995-05-24 |
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| Date | Code | Title | Description |
|---|---|---|---|
| EEER | Examination request | ||
| MKLA | Lapsed |