JPS6410728A - Clock generation circuit - Google Patents

Abstract

PURPOSE:To surely make the phase relation of an output signal constant by making a clear signal outputted from a clear generation circuit, synchronize with a clock signal to be inputted to a frequency divider, when the clear signal is inputted to the frequency divider, at the time of the application of a power supply. CONSTITUTION:After the power supply is applied, a primary clock 2 generated from a primary oscillator 1 is inputted to a 1/2 frequency divider 3, and a positive clock signal 4 and a flip flop clock signal 5 are obtained. On the other hand, the clear signal 13 generated from the clear generation circuit 12 is inputted to a clear synchronizing flip flop 14, and by sampling the clear signal 13 by the positive clock signal 4, a clear synchronizing signal 15 is obtained as a form that the clear signal 13 synchronizes with the positive clock signal 4. The obtained clear synchronizing signal 15 is sent as the initial reset signal of a positive 1/2 frequency divider 6 and a negative 1/2 frequency divider 9. Thus, even if the power supply is applied many times, the phase relation of the output signal can be made always not to change.