JPS55147062A - Frequency modulator - Google Patents
Frequency modulatorInfo
- Publication number
- JPS55147062A JPS55147062A JP5503079A JP5503079A JPS55147062A JP S55147062 A JPS55147062 A JP S55147062A JP 5503079 A JP5503079 A JP 5503079A JP 5503079 A JP5503079 A JP 5503079A JP S55147062 A JPS55147062 A JP S55147062A
- Authority
- JP
- Japan
- Prior art keywords
- integrator
- output
- signal
- input
- initial value
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
Classifications
-
- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
- H04L27/00—Modulated-carrier systems
- H04L27/18—Phase-modulated carrier systems, i.e. using phase-shift keying
- H04L27/20—Modulator circuits; Transmitter circuits
- H04L27/2032—Modulator circuits; Transmitter circuits for discrete phase modulation, e.g. in which the phase of the carrier is modulated in a nominally instantaneous manner
- H04L27/2035—Modulator circuits; Transmitter circuits for discrete phase modulation, e.g. in which the phase of the carrier is modulated in a nominally instantaneous manner using a single or unspecified number of carriers
Landscapes
- Engineering & Computer Science (AREA)
- Computer Networks & Wireless Communication (AREA)
- Signal Processing (AREA)
- Digital Transmission Methods That Use Modulated Carrier Waves (AREA)
Abstract
PURPOSE:To reduce the variation of phase of modulated waves, by setting the initial value of the integrator in synchronizing with the input digital signal with the output in response to the input digital signal up to now and preventing the storage of integrated error. CONSTITUTION:The signal at the input terminal 41 is branched into two; one is input to the integrator 44 via the filter 43 to synchronize with the clock signal fed to the terminal 42 and to reset the initial value of the integration into zero. Another is in synchronizing with the clock signal to produce a given voltage within a given time, and this voltage value is fed to the circuit 45 which changes the value in response to the input digital signal fed up to now. Further, by using the signal adding the output of the integrator 44 with the output of the ciruit 45, phase modulation is made at the phase modulator 47. Accordingly, since the initial value of the integrator 44 is set with the output of the digital circuit 45, the error of integration can not be stored.
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP5503079A JPS55147062A (en) | 1979-05-04 | 1979-05-04 | Frequency modulator |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP5503079A JPS55147062A (en) | 1979-05-04 | 1979-05-04 | Frequency modulator |
Publications (2)
Publication Number | Publication Date |
---|---|
JPS55147062A true JPS55147062A (en) | 1980-11-15 |
JPS6154301B2 JPS6154301B2 (en) | 1986-11-21 |
Family
ID=12987259
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP5503079A Granted JPS55147062A (en) | 1979-05-04 | 1979-05-04 | Frequency modulator |
Country Status (1)
Country | Link |
---|---|
JP (1) | JPS55147062A (en) |
-
1979
- 1979-05-04 JP JP5503079A patent/JPS55147062A/en active Granted
Also Published As
Publication number | Publication date |
---|---|
JPS6154301B2 (en) | 1986-11-21 |
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