JPS56111323A - Synchronizing circuit - Google Patents

Synchronizing circuit

Info

Publication number
JPS56111323A
JPS56111323A JP1394780A JP1394780A JPS56111323A JP S56111323 A JPS56111323 A JP S56111323A JP 1394780 A JP1394780 A JP 1394780A JP 1394780 A JP1394780 A JP 1394780A JP S56111323 A JPS56111323 A JP S56111323A
Authority
JP
Japan
Prior art keywords
output
dividing circuit
frequency dividing
state
dut
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP1394780A
Other languages
Japanese (ja)
Inventor
Fumio Moro
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Seiko Instruments Inc
Original Assignee
Seiko Instruments Inc
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Seiko Instruments Inc filed Critical Seiko Instruments Inc
Priority to JP1394780A priority Critical patent/JPS56111323A/en
Publication of JPS56111323A publication Critical patent/JPS56111323A/en
Pending legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K21/00—Details of pulse counters or frequency dividers
    • H03K21/40—Monitoring; Error detection; Preventing or correcting improper counter operation
    • H03K21/406—Synchronisation of counters

Abstract

PURPOSE:To synchronize frequency dividers mutually without providing any reset terminal, by a frequency dividing circuit which operates at the fall of the ending output wave of another frequency dividing circuit, NAND and AND gates, and a start signal for synchronization. CONSTITUTION:When a start signal changes from state L to state H, ending output Q of MOSLSI (DUT) for a timer is inputted to frequency dividing circuit C and at its fall, output Q' is held in state L to close NAND gate D. Therefore, DUT stops. Then, when output Q of the frequency dividing circuit (REF) falls, output Q of frequency dividing circuit A is placed in state H and when output Q of FEF falls again, output Q of frequency dividing circuit B is held in state H and that of A in state L. Therefore, gate E is turned off and frequency dividing circuit C is reset, so that a pulse will be inputted to DUT again. Next, the start signal is held at L and output Q' of frequency dividing circuit C is held at H. Thus, DUT and REF are synchronized with each other.
JP1394780A 1980-02-07 1980-02-07 Synchronizing circuit Pending JPS56111323A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP1394780A JPS56111323A (en) 1980-02-07 1980-02-07 Synchronizing circuit

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP1394780A JPS56111323A (en) 1980-02-07 1980-02-07 Synchronizing circuit

Publications (1)

Publication Number Publication Date
JPS56111323A true JPS56111323A (en) 1981-09-03

Family

ID=11847394

Family Applications (1)

Application Number Title Priority Date Filing Date
JP1394780A Pending JPS56111323A (en) 1980-02-07 1980-02-07 Synchronizing circuit

Country Status (1)

Country Link
JP (1) JPS56111323A (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4651334A (en) * 1983-12-26 1987-03-17 Hitachi, Ltd. Variable-ratio frequency divider

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4651334A (en) * 1983-12-26 1987-03-17 Hitachi, Ltd. Variable-ratio frequency divider

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