JPS54152828A - Clock synchronous control system - Google Patents

Clock synchronous control system

Info

Publication number
JPS54152828A
JPS54152828A JP6123978A JP6123978A JPS54152828A JP S54152828 A JPS54152828 A JP S54152828A JP 6123978 A JP6123978 A JP 6123978A JP 6123978 A JP6123978 A JP 6123978A JP S54152828 A JPS54152828 A JP S54152828A
Authority
JP
Japan
Prior art keywords
counter
clock
synchronized
timing
constitution
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP6123978A
Other languages
Japanese (ja)
Inventor
Yoichi Hamada
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Toshiba Corp
Original Assignee
Toshiba Corp
Tokyo Shibaura Electric Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Toshiba Corp, Tokyo Shibaura Electric Co Ltd filed Critical Toshiba Corp
Priority to JP6123978A priority Critical patent/JPS54152828A/en
Publication of JPS54152828A publication Critical patent/JPS54152828A/en
Pending legal-status Critical Current

Links

Abstract

PURPOSE:To ensure switching without stopping the operation temporarily by securing a free selective switching from the single to the dual constitution for the operation based on the control signal given from outside. CONSTITUTION:In the case of the dual constitution in which ring counter 1011 and 1012 are actuated in synchronization, #1 counter 1011 of the master side carries out generation of the synchronous clock with supply of fundamental clock signal B- CLK1 at the clock input end. While the clock timing supplied to #2 counter 1012 of the slave side via signal line 105 is synchronized with the timing of clock 1011 through adjustment of delay element 106. At the same time, synchronized signal SY2 timing supplied to counter 1012 is synchronized with the full count output timing with the prescribed count output at the middle part of counter 1011 delayed by signal line 103 and delay element 104. Thus, counter 1012 can generate the clock synchronized with 1011.
JP6123978A 1978-05-23 1978-05-23 Clock synchronous control system Pending JPS54152828A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP6123978A JPS54152828A (en) 1978-05-23 1978-05-23 Clock synchronous control system

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP6123978A JPS54152828A (en) 1978-05-23 1978-05-23 Clock synchronous control system

Publications (1)

Publication Number Publication Date
JPS54152828A true JPS54152828A (en) 1979-12-01

Family

ID=13165472

Family Applications (1)

Application Number Title Priority Date Filing Date
JP6123978A Pending JPS54152828A (en) 1978-05-23 1978-05-23 Clock synchronous control system

Country Status (1)

Country Link
JP (1) JPS54152828A (en)

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