JPS5758433A - Clock synchronizing system - Google Patents

Clock synchronizing system

Info

Publication number
JPS5758433A
JPS5758433A JP55133561A JP13356180A JPS5758433A JP S5758433 A JPS5758433 A JP S5758433A JP 55133561 A JP55133561 A JP 55133561A JP 13356180 A JP13356180 A JP 13356180A JP S5758433 A JPS5758433 A JP S5758433A
Authority
JP
Japan
Prior art keywords
notation
counter
clocks
synchronism
master
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP55133561A
Other languages
Japanese (ja)
Other versions
JPH0152945B2 (en
Inventor
Meiki Yahata
Hideo Suzuki
Shunsuke Yoda
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Toshiba Corp
Original Assignee
Toshiba Corp
Tokyo Shibaura Electric Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Toshiba Corp, Tokyo Shibaura Electric Co Ltd filed Critical Toshiba Corp
Priority to JP55133561A priority Critical patent/JPS5758433A/en
Priority to DE8181107326T priority patent/DE3173313D1/en
Priority to EP81107326A priority patent/EP0048896B1/en
Priority to CA000386657A priority patent/CA1183579A/en
Priority to US06/305,712 priority patent/US4475085A/en
Publication of JPS5758433A publication Critical patent/JPS5758433A/en
Publication of JPH0152945B2 publication Critical patent/JPH0152945B2/ja
Granted legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L7/00—Arrangements for synchronising receiver with transmitter
    • H04L7/02—Speed or phase control by the received code signals, the signals containing no special synchronisation information
    • H04L7/033—Speed or phase control by the received code signals, the signals containing no special synchronisation information using the transitions of the received signal to control the phase of the synchronising-signal-generating means, e.g. using a phase-locked loop
    • H04L7/0331—Speed or phase control by the received code signals, the signals containing no special synchronisation information using the transitions of the received signal to control the phase of the synchronising-signal-generating means, e.g. using a phase-locked loop with a digital phase-locked loop [PLL] processing binary samples, e.g. add/subtract logic for correction of receiver clock

Landscapes

  • Engineering & Computer Science (AREA)
  • Computer Networks & Wireless Communication (AREA)
  • Signal Processing (AREA)
  • Synchronisation In Digital Transmission Systems (AREA)

Abstract

PURPOSE:To use the clocks of a master side and a slave side with synchronism in common, by changing the number of clocks circulating the arithmetic in both sides respectively, in a system functioning on the master and slave sides. CONSTITUTION:An original clock signal is produced from a clock source 31. A variable period counter 33 operates between n-notation and n+ms notation. When a system is operated at the slave side, the period of the counter 33 is changed between the n-notation and the n+ms notation to take synchronism at the master side. The system at the master side drives a digital arithmetic system 39 with clocks produced from a counter 7 having a fixed period. When the counter 7 selectes m-notation (n<m<n+ms), the counter 33 can be operated as m-notation in average through the control of the counter 33 for synchronism.
JP55133561A 1980-09-25 1980-09-25 Clock synchronizing system Granted JPS5758433A (en)

Priority Applications (5)

Application Number Priority Date Filing Date Title
JP55133561A JPS5758433A (en) 1980-09-25 1980-09-25 Clock synchronizing system
DE8181107326T DE3173313D1 (en) 1980-09-25 1981-09-16 Clock synchronization signal generating circuit
EP81107326A EP0048896B1 (en) 1980-09-25 1981-09-16 Clock synchronization signal generating circuit
CA000386657A CA1183579A (en) 1980-09-25 1981-09-25 Clock synchronization signal generating circuit
US06/305,712 US4475085A (en) 1980-09-25 1981-09-25 Clock synchronization signal generating circuit

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP55133561A JPS5758433A (en) 1980-09-25 1980-09-25 Clock synchronizing system

Publications (2)

Publication Number Publication Date
JPS5758433A true JPS5758433A (en) 1982-04-08
JPH0152945B2 JPH0152945B2 (en) 1989-11-10

Family

ID=15107676

Family Applications (1)

Application Number Title Priority Date Filing Date
JP55133561A Granted JPS5758433A (en) 1980-09-25 1980-09-25 Clock synchronizing system

Country Status (1)

Country Link
JP (1) JPS5758433A (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS62185865A (en) * 1986-02-13 1987-08-14 Nippon Steel Corp Manufacture of hot dip aluminized steel sheet having superior corrosion resistance

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS62185865A (en) * 1986-02-13 1987-08-14 Nippon Steel Corp Manufacture of hot dip aluminized steel sheet having superior corrosion resistance
JPH0261543B2 (en) * 1986-02-13 1990-12-20 Nippon Steel Corp

Also Published As

Publication number Publication date
JPH0152945B2 (en) 1989-11-10

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