JPS5787643A - Clock controlling system - Google Patents

Clock controlling system

Info

Publication number
JPS5787643A
JPS5787643A JP55164204A JP16420480A JPS5787643A JP S5787643 A JPS5787643 A JP S5787643A JP 55164204 A JP55164204 A JP 55164204A JP 16420480 A JP16420480 A JP 16420480A JP S5787643 A JPS5787643 A JP S5787643A
Authority
JP
Japan
Prior art keywords
clock
basic clock
circuit
basic
transmission line
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP55164204A
Other languages
Japanese (ja)
Other versions
JPS6058617B2 (en
Inventor
Teruo Aizawa
Minoru Etsuno
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Fujitsu Ltd
Original Assignee
Fujitsu Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Fujitsu Ltd filed Critical Fujitsu Ltd
Priority to JP55164204A priority Critical patent/JPS6058617B2/en
Publication of JPS5787643A publication Critical patent/JPS5787643A/en
Publication of JPS6058617B2 publication Critical patent/JPS6058617B2/en
Expired legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L7/00—Arrangements for synchronising receiver with transmitter

Landscapes

  • Engineering & Computer Science (AREA)
  • Computer Networks & Wireless Communication (AREA)
  • Signal Processing (AREA)
  • Synchronisation In Digital Transmission Systems (AREA)

Abstract

PURPOSE:To simply obtain clock synchronization with different speeds, by obtaining a clock with period equivalent to an integer multiple of the basic clock, through the logical product between the basic clock and the period signal having the period equivalent to an integer multiple of the basic clock. CONSTITUTION:The basic clock of a basic closk generating section 1 is transmitted to a device II' via a transmission line (c), the output of the frequency division circuit 2 is to the deviceIvia a transmission line (a), and a sunchronizing signal of a synchronizing signal circuit 18 is to the device II' via a transmission line (d), respectively. The basic clock via inverters 19, 21 and the synchronizing signal via an FF24 are inputted to an AND circuit 25, and the output controls an FF27. The basic clock via the inverters 19, 20 and the synchronizing signal via the FF24 are inputted to an AND circuit 26, and the output controls the FF28. Thus, the FFs 6, 7 and the FFs 27, 28 can be operated in synchronization with each other.
JP55164204A 1980-11-21 1980-11-21 Clock control method Expired JPS6058617B2 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP55164204A JPS6058617B2 (en) 1980-11-21 1980-11-21 Clock control method

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP55164204A JPS6058617B2 (en) 1980-11-21 1980-11-21 Clock control method

Publications (2)

Publication Number Publication Date
JPS5787643A true JPS5787643A (en) 1982-06-01
JPS6058617B2 JPS6058617B2 (en) 1985-12-20

Family

ID=15788641

Family Applications (1)

Application Number Title Priority Date Filing Date
JP55164204A Expired JPS6058617B2 (en) 1980-11-21 1980-11-21 Clock control method

Country Status (1)

Country Link
JP (1) JPS6058617B2 (en)

Also Published As

Publication number Publication date
JPS6058617B2 (en) 1985-12-20

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