JPS55134544A - Phase-synchronous oscillator - Google Patents

Phase-synchronous oscillator

Info

Publication number
JPS55134544A
JPS55134544A JP4133579A JP4133579A JPS55134544A JP S55134544 A JPS55134544 A JP S55134544A JP 4133579 A JP4133579 A JP 4133579A JP 4133579 A JP4133579 A JP 4133579A JP S55134544 A JPS55134544 A JP S55134544A
Authority
JP
Japan
Prior art keywords
circuit
break
output signal
output
dividing circuit
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP4133579A
Other languages
Japanese (ja)
Inventor
Haruo Tsuda
Takayuki Okino
Toshio Iyota
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Fujitsu Ltd
Original Assignee
Fujitsu Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Fujitsu Ltd filed Critical Fujitsu Ltd
Priority to JP4133579A priority Critical patent/JPS55134544A/en
Publication of JPS55134544A publication Critical patent/JPS55134544A/en
Pending legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03L—AUTOMATIC CONTROL, STARTING, SYNCHRONISATION OR STABILISATION OF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES
    • H03L7/00—Automatic control of frequency or phase; Synchronisation
    • H03L7/06—Automatic control of frequency or phase; Synchronisation using a reference signal applied to a frequency- or phase-locked loop
    • H03L7/08—Details of the phase-locked loop
    • H03L7/14—Details of the phase-locked loop for assuring constant frequency when supply or correction voltages fail or are interrupted
    • H03L7/143—Details of the phase-locked loop for assuring constant frequency when supply or correction voltages fail or are interrupted by switching the reference signal of the phase-locked loop
    • H03L7/145—Details of the phase-locked loop for assuring constant frequency when supply or correction voltages fail or are interrupted by switching the reference signal of the phase-locked loop the switched reference signal being derived from the controlled oscillator output signal
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03L—AUTOMATIC CONTROL, STARTING, SYNCHRONISATION OR STABILISATION OF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES
    • H03L7/00—Automatic control of frequency or phase; Synchronisation
    • H03L7/06—Automatic control of frequency or phase; Synchronisation using a reference signal applied to a frequency- or phase-locked loop
    • H03L7/08—Details of the phase-locked loop
    • H03L7/14—Details of the phase-locked loop for assuring constant frequency when supply or correction voltages fail or are interrupted
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03L—AUTOMATIC CONTROL, STARTING, SYNCHRONISATION OR STABILISATION OF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES
    • H03L2207/00—Indexing scheme relating to automatic control of frequency or phase and to synchronisation
    • H03L2207/18—Temporarily disabling, deactivating or stopping the frequency counter or divider

Landscapes

  • Synchronisation In Digital Transmission Systems (AREA)
  • Stabilization Of Oscillater, Synchronisation, Frequency Synthesizers (AREA)

Abstract

PURPOSE:To make use of an oscillator effectively for a network synchronizier on the slave synchronization system, etc., by eliminating the creation of a disturbance in the output signal of a break detecting circuit due to the instantaneous break of an input signal, by stopping the operation of an output-side dividing circuit by the output signal of the break detecting circuit. CONSTITUTION:Break detecting circuit 6 is provided. Once the break of input signal (a) occurs, 1/n dividing circuit 4 stops counting. Simultaneously, circuit 6 geneerates its output of ''1'' to close AND gate 8, making 1/193 dividing circuit 9 stop counting. Selecting circuit 7, on the other hand, selects the output signal of 1/386 dividing circuit 10 by the output signal of circuit 6 and inputs it to LPF2.
JP4133579A 1979-04-05 1979-04-05 Phase-synchronous oscillator Pending JPS55134544A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP4133579A JPS55134544A (en) 1979-04-05 1979-04-05 Phase-synchronous oscillator

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP4133579A JPS55134544A (en) 1979-04-05 1979-04-05 Phase-synchronous oscillator

Publications (1)

Publication Number Publication Date
JPS55134544A true JPS55134544A (en) 1980-10-20

Family

ID=12605642

Family Applications (1)

Application Number Title Priority Date Filing Date
JP4133579A Pending JPS55134544A (en) 1979-04-05 1979-04-05 Phase-synchronous oscillator

Country Status (1)

Country Link
JP (1) JPS55134544A (en)

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5923926A (en) * 1982-07-30 1984-02-07 Fujitsu Ltd Phase locked loop circuit
JPS643338U (en) * 1987-06-23 1989-01-10
JPH0239623A (en) * 1988-07-28 1990-02-08 Nec Corp Pll circuit

Cited By (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5923926A (en) * 1982-07-30 1984-02-07 Fujitsu Ltd Phase locked loop circuit
JPH0324818B2 (en) * 1982-07-30 1991-04-04 Fujitsu Ltd
JPS643338U (en) * 1987-06-23 1989-01-10
JPH0239623A (en) * 1988-07-28 1990-02-08 Nec Corp Pll circuit

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