JPS6432543A - Multiplexing circuit - Google Patents

Abstract

PURPOSE:To multiplex 2<n-1> sets of signals in parallel with multiplexing of 2 signals by applying frequency division of 1/2<n> to a clock signal equal to a frequency of a multiplexed high speed signal with respect to 2<n> sets of signals to be multiplexed so as to use the clock subject to frequency-division. CONSTITUTION:A high-order group clock signal 31 in an input signal to be multiplexed by a multiplex circuit is subject to 1/4 frequency division by two FFs 11, 12 to output clock signals 32-35 with a phase deviation. Moreover, a proper delay is given to low-order group data signals 61-64 and the signals 61-64 are given to NOR gates 51-54 together with the signals 32, 34 outputted from the FF 11 to output RZ data signals 65-68. Then output signals 33, 35 of the FF 12 are given to OR gates 56, 57 together with the signals 65, 66 and 67, 68 to output multiplexed signals 69, 70 of the low-order group data signals 61-64. The signals 69, 70 are given to the NOR gate 55 to output a high-order group data signal 71.