JPS6473929A - Multiplexing circuit - Google Patents

Multiplexing circuit

Info

Publication number
JPS6473929A
JPS6473929A JP23178987A JP23178987A JPS6473929A JP S6473929 A JPS6473929 A JP S6473929A JP 23178987 A JP23178987 A JP 23178987A JP 23178987 A JP23178987 A JP 23178987A JP S6473929 A JPS6473929 A JP S6473929A
Authority
JP
Japan
Prior art keywords
low speed
order
speed data
circuit
parallel
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP23178987A
Other languages
Japanese (ja)
Inventor
Tomoyuki Otsuka
Masaaki Kawai
Shoji Kitagawa
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Fujitsu Ltd
Original Assignee
Fujitsu Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Fujitsu Ltd filed Critical Fujitsu Ltd
Priority to JP23178987A priority Critical patent/JPS6473929A/en
Publication of JPS6473929A publication Critical patent/JPS6473929A/en
Pending legal-status Critical Current

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Landscapes

  • Time-Division Multiplex Systems (AREA)

Abstract

PURPOSE:To make the sequence of each low speed data in multiplexed signals regardless of the application state of power supply by converting a parallel low speed data of an n-channel into a serial signal synchronously with a high speed data in the order decided depending on the count output of a frequency divider circuit applying 1/n frequency division to the high speed clock. CONSTITUTION:The high speed clock is subject to 1/n frequency division via a frequency division circuit 11 to generate a low-order and a high-order count output deciding the order in converting the input parallel low speed data into a serial signal in a parallel/serial conversion circuit 1 and in such a case, a set circuit 4 sets a constant state the frequency divider circuit 11 in response to the low speed clock. Thus, the parallel serial conversion circuit 1 makes the order of each low speed data in the multiplexed signal constant and the order of each low speed based on the low speed data is made always constant even when each circuit is in any state at application of power.
JP23178987A 1987-09-16 1987-09-16 Multiplexing circuit Pending JPS6473929A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP23178987A JPS6473929A (en) 1987-09-16 1987-09-16 Multiplexing circuit

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP23178987A JPS6473929A (en) 1987-09-16 1987-09-16 Multiplexing circuit

Publications (1)

Publication Number Publication Date
JPS6473929A true JPS6473929A (en) 1989-03-20

Family

ID=16929047

Family Applications (1)

Application Number Title Priority Date Filing Date
JP23178987A Pending JPS6473929A (en) 1987-09-16 1987-09-16 Multiplexing circuit

Country Status (1)

Country Link
JP (1) JPS6473929A (en)

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