JPS5758435A - Clock synchronizing system - Google Patents

Clock synchronizing system

Info

Publication number
JPS5758435A
JPS5758435A JP55133563A JP13356380A JPS5758435A JP S5758435 A JPS5758435 A JP S5758435A JP 55133563 A JP55133563 A JP 55133563A JP 13356380 A JP13356380 A JP 13356380A JP S5758435 A JPS5758435 A JP S5758435A
Authority
JP
Japan
Prior art keywords
clock
clock signals
original clock
original
notation
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP55133563A
Other languages
Japanese (ja)
Inventor
Meiki Yahata
Hideo Suzuki
Shunsuke Yoda
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Toshiba Corp
Original Assignee
Toshiba Corp
Tokyo Shibaura Electric Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Toshiba Corp, Tokyo Shibaura Electric Co Ltd filed Critical Toshiba Corp
Priority to JP55133563A priority Critical patent/JPS5758435A/en
Priority to DE8181107326T priority patent/DE3173313D1/en
Priority to EP81107326A priority patent/EP0048896B1/en
Priority to CA000386657A priority patent/CA1183579A/en
Priority to US06/305,712 priority patent/US4475085A/en
Publication of JPS5758435A publication Critical patent/JPS5758435A/en
Pending legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L7/00—Arrangements for synchronising receiver with transmitter
    • H04L7/02—Speed or phase control by the received code signals, the signals containing no special synchronisation information
    • H04L7/033—Speed or phase control by the received code signals, the signals containing no special synchronisation information using the transitions of the received signal to control the phase of the synchronising-signal-generating means, e.g. using a phase-locked loop
    • H04L7/0331—Speed or phase control by the received code signals, the signals containing no special synchronisation information using the transitions of the received signal to control the phase of the synchronising-signal-generating means, e.g. using a phase-locked loop with a digital phase-locked loop [PLL] processing binary samples, e.g. add/subtract logic for correction of receiver clock

Landscapes

  • Engineering & Computer Science (AREA)
  • Computer Networks & Wireless Communication (AREA)
  • Signal Processing (AREA)
  • Synchronisation In Digital Transmission Systems (AREA)

Abstract

PURPOSE:To take clock synchronism at all times, by changing the number of clocks required for circulation of operation through the use of a variable period counter and changing the number of clocks in average continuously. CONSTITUTION:When a slave side system circulated an operation with 4 or 5 original clock signals, the operation of a master side system is circulated with 4 original clock signals or 5 original clock signals alternately or at random, allowing to circulate the operation with 4.5 original clock signals in average. Thus, even if the master side has a position of the slave side, the synchronism can almost be achieved. 4-notation and 5-notation can be switched by a control circuit 34 in a variable period counter 33 within a clock synchronizing circuit 32. A control circuit 38 in a clock circuit 36 produces a signal which can change the clock at random.
JP55133563A 1980-09-25 1980-09-25 Clock synchronizing system Pending JPS5758435A (en)

Priority Applications (5)

Application Number Priority Date Filing Date Title
JP55133563A JPS5758435A (en) 1980-09-25 1980-09-25 Clock synchronizing system
DE8181107326T DE3173313D1 (en) 1980-09-25 1981-09-16 Clock synchronization signal generating circuit
EP81107326A EP0048896B1 (en) 1980-09-25 1981-09-16 Clock synchronization signal generating circuit
CA000386657A CA1183579A (en) 1980-09-25 1981-09-25 Clock synchronization signal generating circuit
US06/305,712 US4475085A (en) 1980-09-25 1981-09-25 Clock synchronization signal generating circuit

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP55133563A JPS5758435A (en) 1980-09-25 1980-09-25 Clock synchronizing system

Publications (1)

Publication Number Publication Date
JPS5758435A true JPS5758435A (en) 1982-04-08

Family

ID=15107722

Family Applications (1)

Application Number Title Priority Date Filing Date
JP55133563A Pending JPS5758435A (en) 1980-09-25 1980-09-25 Clock synchronizing system

Country Status (1)

Country Link
JP (1) JPS5758435A (en)

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