JPS53108207A - Control system for frame synchronous circuit - Google Patents

Control system for frame synchronous circuit

Info

Publication number
JPS53108207A
JPS53108207A JP2316977A JP2316977A JPS53108207A JP S53108207 A JPS53108207 A JP S53108207A JP 2316977 A JP2316977 A JP 2316977A JP 2316977 A JP2316977 A JP 2316977A JP S53108207 A JPS53108207 A JP S53108207A
Authority
JP
Japan
Prior art keywords
control system
synchronous circuit
frame synchronous
frame
discrepancy
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP2316977A
Other languages
Japanese (ja)
Inventor
Ikuo Kodama
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
NEC Corp
Original Assignee
NEC Corp
Nippon Electric Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by NEC Corp, Nippon Electric Co Ltd filed Critical NEC Corp
Priority to JP2316977A priority Critical patent/JPS53108207A/en
Publication of JPS53108207A publication Critical patent/JPS53108207A/en
Pending legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04J—MULTIPLEX COMMUNICATION
    • H04J3/00—Time-division multiplex systems
    • H04J3/02—Details
    • H04J3/06—Synchronising arrangements
    • H04J3/062—Synchronisation of signals having the same nominal but fluctuating bit rates, e.g. using buffers
    • H04J3/0626—Synchronisation of signals having the same nominal but fluctuating bit rates, e.g. using buffers plesiochronous multiplexing systems, e.g. plesiochronous digital hierarchy [PDH], jitter attenuators

Abstract

PURPOSE:To prevent the discrepancy of the frame synchronization caused by slip, by controlling the elastic memory under the specified phase state of the frame counter.
JP2316977A 1977-03-02 1977-03-02 Control system for frame synchronous circuit Pending JPS53108207A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP2316977A JPS53108207A (en) 1977-03-02 1977-03-02 Control system for frame synchronous circuit

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP2316977A JPS53108207A (en) 1977-03-02 1977-03-02 Control system for frame synchronous circuit

Publications (1)

Publication Number Publication Date
JPS53108207A true JPS53108207A (en) 1978-09-20

Family

ID=12103110

Family Applications (1)

Application Number Title Priority Date Filing Date
JP2316977A Pending JPS53108207A (en) 1977-03-02 1977-03-02 Control system for frame synchronous circuit

Country Status (1)

Country Link
JP (1) JPS53108207A (en)

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS62146035A (en) * 1985-12-18 1987-06-30 インタ−ナショナル　ビジネス　マシ−ンズ　コ−ポレ−ション Data synchronizer
JP2007306362A (en) * 2006-05-12 2007-11-22 Hitachi Kokusai Electric Inc Communication apparatus

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS62146035A (en) * 1985-12-18 1987-06-30 インタ−ナショナル　ビジネス　マシ−ンズ　コ−ポレ−ション Data synchronizer
JP2007306362A (en) * 2006-05-12 2007-11-22 Hitachi Kokusai Electric Inc Communication apparatus

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