SU1660175A1 - Series-to-parallel code converter - Google Patents

Abstract

The invention relates to computing and can be used in information transmission systems. The invention makes it possible to eliminate unauthorized device failures when processing large amounts of information and re-processing it, which improves the noise immunity of the device. The device contains a shift register 1, a generator of 2 clock pulses, the elements AND-NO 3 - 6 and the element NOT 7. 2 Il.

Description

The invention relates to computing and can be used in information transmission systems.

The aim of the invention is to improve the noise immunity of the device.

Fig. 1 is a functional block diagram of the device; Fig. 2 is a timing diagram for explaining the operation of the device.

A device for converting a serial code into a parallel one contains a shift register 1, a generator of 2 clock pulses, the first to fourth elements of NAND and NOT element 7, information input 8 and start input 9, first 10 and second 11 outputs.

Fig 2 shows the signal plots a - at the start-up input, b - at the output of the generator 2; in - at the output of the element b; Mr. output element 5; d - at the first output device, e - signal at its second output.

The device works as follows.

The algorithm works with the correct reception of information.

Input 9 receives a preset signal at time to, with the first bit of shift register 1 being set to state 1, and the remaining bits being set to state O At the output of the (n + 1) -th bit of shift register 1, signal O is set , and the output of the element IS-HE 4 (output 10) also sets the signal O. Signals O from outputs 11 and 10 are sent to the generator 2 clock pulses and serve as a signal for an external transmitter of information on readiness to receive information

At the moment c, the information transmitter starts transmitting information and at the input 8 information appears at the generator output 2 clock pulses - synchronization pulses. The leading edge of the first pulse sets the output of the AND-NE element 4 to state 1 through the IS-NOT element 3. Inverted element AND-NOT 3, arrive at the clock input of the shift register 1 and record information

ON Oh

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The mapping arriving at the input 8 of the shift register 1, with a simultaneous shift of this information at its discharge. In the case of receiving the expected n bits of a sequential code without a failure (where n is the number of information bits contained in the received word), the (n + 1) th bit of the shift register 1 is written 1, shifted by n clock pulses from the 1st bit register shift 1. At the same time, signal 1 is set at output 11. Signal 1 remains at output 10, because although the enable signal 1 arrives at the first output of the AND-NOT element 6, a reset 1 at output 10 does not occur due to the end of the burst of clock pulses and the reset signal at the output of the element AND-NOT 6 and the output of the element AND-NOT 5, i.e. The outputs 11 are set to signals 11, indicating that the word has been correctly received. To receive the next word, an impulse must be applied at input 9, and the process is repeated.

The algorithm works when the reception of information such as an extra shift.

The launch of the device is carried out as described.

As information arrives, malfunction may occur, whereby information is shifted by impulsive noise without affecting clock pulses, the signal 1, previously recorded in the first bit of shift register 1, is in (n + 1) -th shift de register 1 of shift at that moment when at the generator output 2 clock pulses the burst of sync pulses is not over yet. Consider the operation of the system from this point on, the admission that there was a shift of one extra cycle. In this case, 1 is recorded in the (n + 1) -th bit of the shift register de 1-a (n-1) -th pulse of a burst of sync pulses. At the same time, the signal 1, which arrives from the (n + 1) -th bit of register 1 through the NOT 7 element, prohibits further passage of clock pulses (in this case, one nth pulse remains) to the clock input of shift register 1 and allows clock pulses (in this case, the n-th) through the element AND-NOT 6 to the element AND-NOT 5. From the generator output 2 clock pulses, the n-th clock pulse through the elements AND-NOT 6 and 5 sets the output of the element AND-NOT 4 to the state A. At the same time, state 10 is set at outputs 11 and 10, which indicates a malfunction and reception of information and type an extra shift. Similarly, the device works with a greater number of clock cycles. With

The remaining pulses from the burst of sync pulses only confirm the signal state O at the output 10 of the device.

The operation algorithm in case of a failure in receiving information such as the missing shift.

The launch of the device is carried out as described.

As information arrives, individual pulses may fall out of the burst of clock pulses, while the shift register 1 does not record the information corresponding to the missing clock pulse, and information 1, previously recorded in the first shift of the shift register 1, will not shift to +1) - th bit of register shift 1.

In this case, in the (n + 1) th discharge of the register

Is the shift after the end of the burst of sync pulses coming from the generator 2 pulses, the signal O is lost, and at the outputs

I1 and 10 remain state 01, which corresponds to the failure to receive information such as the missing shift.

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Claims (1)

Invention Formula A device for converting a serial code into a parallel one, comprising a clock pulse generator and the shift register, the information input of which is the information input of the device, and the installation input is the start input of the device, characterized in that, in order to increase noise immunity of the device, in the elements of the elements NAND and the element NOT, the output which is connected to the first input of the first NAND element, the output of which is connected to the clock input of the shift register and the first input of the second NAND element, the output of which is connected to the first inputs of the third NAND element and the clock, and is the first output of the device, the output of the shift register connected to the input of the element NOT, to the first input of the fourth element NAND, to the second input of the clock generator, and is the second output of the device, the output of the generator of clock pulses is connected to the second inputs of the first and fourth elements AND-NOT. the output of the fourth element AND-NOT is connected to the second input of the third element AND-NOT, the output of which is connected to the second input of the second element AND-NOT, the third input of the third element AND-NO is combined with the setting input of the shift register. r-g TAGILG l g-ii FIG. 2