SU1262732A1 - Sequential code-to-parallel code converter - Google Patents

Abstract

The invention relates to computing technology, namely, information converting devices, and can be used in data transmission systems over digital channels. The device allows not only to determine failures in the reception of information over the channel and to enter a word as. the reception of which failed, but also during the transition from channel to channel during asynchronous information transfer, to reveal unreliable words and exclude them from further use. In addition, the device provides operation with various bits of serial and parallel codes. All of the above expands the functionality of the device and increases the reliability of the processed information. The serial to parallel converter contains a shift register, a buffer register, a control block, and a pause block. The first and second pause block inputs are a sync input and a sync pulse input for a device code, respectively. The third input of the shift register is the information input of the device. The output is bu (the Led register and the second output of the control unit are, respectively, the output of the device and an additional output. The control unit consists of a decoder, a delay element of two pulse conditioners. A pause allocation block consists of 5 counters of a pulse counter, two elements And NOT. 2 Cp f-crystals, U 3 or. SO yu

Description

The invention relates to computing and can be used in data transmission systems over digital channels.

The aim of the invention is to increase the reliability of the information to be converted and to expand the area of application: by converting a code of various bits.

FIG. 1 shows a functional diagram of the device; Fig 2 is a functional block diagram of the control unit; in fig. 3 - functional block of the block pause.

The serial to parallel converter contains a shift register 1, a buffer register 2, a control unit 3, a pause allocation unit 4, the first input of which is device sync input 5, and the second input is input 6 of device code sync pulses. The output of buffer register 2 is device output 7. The third input of the shift register 1 is the information input 8 of the device. The second output of control unit 3 is an additional output 9 of the device.

The control unit 3 comprises a decoder to, a first pulse shaper 11, a delay element 12 and a second pulse shaper 13.

The pause allocation unit 4 comprises a pulse counter 14, the first element AND 15, the element NOT 16 and the second element And 17.

The device works as follows.

The first input of the pause allocation unit 4 from input 5 receives reference clock pulses with a frequency close to the code clock frequency received from input 6, Counter 14 calculates clock pulses that passed through the C17 element, and periodically zeroed the code clock pulses. If there are no sync pulses, which corresponds to a pause in the reception of a sequential code, then counter 14 counts the reference sync pulses at the output of the AND 17 element, i.e. sequentially generates bits of the binary code that arrive at the elements of AND 15 and the element of HE 16 and successively form a pause pulse and a signal to prohibit counting. The signal to prohibit the count arrives at the element And 17 and prohibits the passage of the reference clock pulses to the counter 14.

If there are code sync pulses, which is consistent with the reception of a sequential code, then the counter 14 periodically zeroes at the code clock frequency, which is close to the base clock frequency, and pause pulses are not generated. The pause pulse overwrites the information bits from shift register 1 to buffer register 2.

The impulse of the initial setup from the output of the control unit 3 is fed to the input of the initial setup of the shift register 1 and produces its initial: in the lower bit of the registrar 1, the shift is written down 1, and in all other (2 - n + -2) bits - O.

As the sequential code and clock pulses are received on the shift register 1, information on input 8 is received.

When a channel is changed in multichannel information transmission systems by a serial code, the number of code clock pulses between two adjacent pause pulses can vary in the range from 1 to 2 N at the nominal size of the serial code n N.

In this regard, there are three cases of operation of the device for converting a serial code into a parallel one: the number of code pulses is equal to nominal (n N); the number of code pulses is less than the nominal (n N) ;. the number of code pulses is greater than the nominal (n N),

Claims (1)

If the number of sync pulses is equal to the nominal, then in the complementary bits (n + 1) and (n + 2) of the shift register 1 there is a 10% recorded code which goes to the decoder 10 of the state of the additional bits of the control 3, the pause pulse is triggered by the driver 11 and an impulse is generated which speaks of the end of the reception and of the reliability of the received information. The pause pulse is delayed by the delay element 12 at the non-time. walked to confidently rewrite information from the shift register 1 to the buffer register 2, and goes to pulse generator 13, where the initial setup pulse is generated. If the number of sync pulses is less than the nominal, then in additional bits (n + 1) and (n + 2) of shift register 1, code 00 is written, which goes to the decoder 10 of control block 3 and pause pulses, driver 11 does not start and the end signal no conversion is formed. A pause pulse is supplied to the driver 13 where the initial pulse is formed. installation. If the number of sync pulses of the code is more than the nominal, then as soon as the additional bit (n + 2) of the shift register 1 contains the recorded code 1, which goes to the decoder 10 of the control block 3 and causes the generator 13 to start and the generator 1 is disabled. the initial setup pulse formation is carried out by the control unit 3 in the presence of an i-pulse or in the presence of (n + 2) additional discharge of register 1 of code 1 shift. The use of the received information is carried out only at Formation formed at output 9, Claim 1. Inverter of a sequential code into a parallel one, containing a shift register, characterized in that, in order to increase the reliability and expand the scope of application by converting a code of various bits, a buffer register, block control unit and pause unit, the output of which is connected to the control inputs of the buffer register and control unit, n information outputs of the shift register are connected to the corresponding information inputs of the buffer A pivot register whose output is a device output (n + 1) and (n + 2) of the shift register outputs is connected to the information inputs of the control unit, the first output of which is connected to the first input of the shift register, and the second output is the additional output of the device the first input of the pause allocation unit is the synchronization input of the device, and the second input is combined with the second input of the shift register and is the input of the device code clock, the third input of the shift register is the information input of the device. 2, the converter according to claim 1, characterized in that the control unit comprises a decoder, a first pulse shaper, a delay element and a second pulse shaper, the input of which is connected to the output of the delay element, the input of which is connected to the first output of the decoder; the second output of which is connected to the input of the first pulse generator, the first and second inputs of the decoder are respectively the control input and the information input of the control unit, the outputs of the first and second pulse shapers are respectively n rvym and second outputs of the control unit. 3. The converter according to claim 1, characterized in that the block pause includes a pulse counter, the first element is AND, the element is NOT and the second element is And the output of which is connected to the counting input of the pulse counter, the output of the highest bit of which is NOT connected to the first input of the second element AND, the low-order outputs of the pulse counter are connected to the corresponding inputs of the first element AND whose output is the output of the pause input unit, the second input of the second element AND and the installation input of the pulse counter are respectively It is the first and second inputs of the pause allocation unit. FIG. g