JP2010166248A - Communicating system - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide an inexpensive communication system which surely and easily sets addresses of respective terminal devices. <P>SOLUTION: The communication system is provided with a plurality of terminal devices in which inherent addresses are set, and a terminal management device for identifying addresses of the plurality of terminal devices to communicate with the plurality of terminal devices wherein the plurality of terminal devices include decoding parts for decoding address signals inputted from the terminal management device or a terminal device of a preceding stages, a setting part for setting the addresses obtained from decoding parts in their own terminal devices, and an outputting part for outputting an address signal showing an address different from the addresses set in their own terminal devices to a terminal device of a succeeding stage. <P>COPYRIGHT: (C)2010,JPO&INPIT

Description

  The present invention relates to a communication system.

  There is known a communication system including a plurality of terminal devices in which unique addresses are set, and a terminal management device that communicates with the terminal devices while identifying addresses of these terminal devices. As an example of this communication system, a plurality of computers each collecting operation information of a plurality of game machines constitute a plurality of terminal devices, and an island computer collecting a plurality of operation information collected by each of the plurality of computer computers is a terminal. There is a communication system of amusement islands constituting the management device (see, for example, Patent Document 1).

  With reference to FIG. 5, a configuration example of the communication system 90 of one game island among a plurality of game islands constituting the game hall will be described. 2 is a block diagram showing a configuration example of the communication system 90. A plurality of computer bases 92 and one island computer 91 are connected via a bus communication wiring 94 to constitute a communication system 90 on the game island. Here, the base computer 92 collects the operation information of the game stand 93, and the island computer 91 totals the operation information collected by all the base computers 92 in the game island. Further, the island computer 91 transmits the total information to the hall computer 1 that controls the inside of the game hall. Note that a plurality of communication systems 90 for a plurality of game islands (not shown) and one hall computer 1 are further connected to constitute a communication system 9 for the entire game hall.

  According to the figure, each computer 92 includes, for example, an address setting switch 927 for setting its own address (see enlarged view). Each computer 92 has, for example, eight sets of lines 922 and 923 that branch out from the CPU 921 into two, and a ground side line 926 to which each of the eight lines 922 is connected via eight address setting switches 927. Each of the eight lines 923 includes an address setting circuit composed of a power supply side line 924 connected via eight pull-up resistors 925. The address setting switch 927 is, for example, a digital switch or a dip switch.

  In the plurality of computers 92, for example, different numbers up to two digits can be generated through ON / OFF setting of eight address setting switches 927, and these numbers can be used as respective addresses.

Japanese Patent Laid-Open No. 8-66536

  However, the above-described communication system 90 in FIG. 5 has a problem that the cost is increased because it is necessary to mount an address setting circuit including an expensive address setting switch 927 for every computer 92 in the game island.

  Further, the address setting switch 927 is manually set by, for example, an administrator for all the computer bases 92. Therefore, as the number of the computer bases 92 increases, the work load increases and the address is set due to a setting error. There is a problem that accidents such as duplication easily occur.

  The problem of the communication system 90 on the amusement island has been described above, but the same problem occurs in a general communication system in which the base computer 92 and the island computer 91 are replaced with the terminal device and the terminal management device described at the beginning, respectively. .

  The present invention has been made in view of such problems, and an object of the present invention is to provide a low-cost communication system in which the address of each terminal device can be set reliably and easily.

  The invention for solving the problem includes a plurality of terminal devices in which unique addresses are set, and a terminal management device that identifies addresses of the plurality of terminal devices and communicates with the plurality of terminal devices, Each of the plurality of terminal devices is a decoding unit that decodes an address signal input from the terminal management device or the preceding terminal device, and a setting unit that sets an address obtained from the decoding unit in its own terminal device, The communication system includes an output unit that outputs an address signal indicating an address different from an address set in the terminal device to the terminal device in the next stage.

  According to this communication system, starting from the address of the address signal output from the terminal management device, different addresses are automatically set for each of the plurality of terminal devices in the connection order of the terminal devices. As a result, the cost can be reduced to the extent that it is not necessary to mount an address setting switch or the like on each terminal device, and the setting is reliable and easy because no human system is involved in the address setting.

  In the communication system, it is preferable that the output unit outputs an address signal indicating an address obtained by adding a predetermined value to an address value set in the terminal device to the next terminal device.

  According to this communication system, the address is number information whose value increases in the order of connection of a plurality of terminal devices, so the structure of data representing each address can be simplified. This leads to a reduction in the capacity of the memory for storing the address, for example, leading to a reduction in cost.

  In the communication system, the address signal has a number of pulse signals corresponding to the value of the address, and the decoding unit assigns the address obtained based on the number of changes of the pulse signal to the setting unit. Preferably, the output unit outputs an address signal having a number of pulse signals corresponding to an address value obtained by adding a predetermined value to the address value to the next-stage terminal device.

  According to this communication system, the address can be reliably set by determining the value of the address based on the number of changes of the pulse signal.

  ADVANTAGE OF THE INVENTION According to this invention, the low-cost communication system which can set the address of each terminal device reliably and easily can be provided.

It is a block diagram which shows the structural example of the communication system of this Embodiment. It is a flowchart which shows an example of the address setting process sequence of the stand computer of this Embodiment. It is a flowchart which shows an example of the switching procedure of the address setting process and communication process of the stand computer of this Embodiment. It is a schematic diagram which shows an example of the address signal input into the stand computer of this Embodiment, and the address signal output from the stand computer. It is a block diagram which shows the structural example of a communication system.

  A configuration example of a communication system 10 according to the present embodiment will be described with reference to FIG. In addition, the figure is a block diagram which shows the structural example of the communication system 10 of this Embodiment.

  As illustrated in FIG. 1, the communication system 10 includes a plurality of computers (terminal devices) 12 and one island computer (terminal management device) 11.

  The base computer 12 is set with a unique address (for example, “01”, “01”, “03”, etc.), receives the operation information from the game table 13, and transmits the operation information to the island computer 11. Specifically, the table computer 12 includes a CPU (decoding unit, setting unit, output unit) 121, a communication interface 122 for communicating with the island computer 11, a communication interface 129 for communicating with the game table 13, A ROM 125, a RAM (setting unit) 126, a timer 127, and a counter 128 are provided. Here, the ROM 125 stores, for example, a program that defines the processing procedure of the CPU 121 in transmission / reception of operation information, and the RAM 126 stores, for example, operation information, a unique address, and the like. For example, the timer 127 measures a reference time for determining the time widths of various pulses constituting an address signal described later, and the counter 128 counts the number of changes of the pulse signal described later, for example.

  The island computer 11 receives the operation information from each of the plurality of computer computers 12, aggregates the operation information, and transmits the aggregation information as a result of the aggregation to the hall computer (not shown). Specifically, the island computer 11 includes a CPU 111 and a communication interface 112 for communicating with the base computer 12. Note that a storage device and the like further included in the island computer 11 are omitted for convenience of illustration.

  Further, as illustrated in the figure, first, the communication interface 112 of the island computer 11 and the terminal IN of the base computer 12 having the address “01” are connected by a wire 141 for bus communication. Inside the base computer 12 at the address “01”, the wiring 141a and the wiring 141b branch from the terminal IN, one wiring 141b is connected to the communication interface 122, and the other wiring 141a is connected to the terminal OUT. . Next, the terminal OUT of the base computer 12 at the address “01” and the terminal IN of the base computer 12 at the address “02” are connected by a wiring 141. Similarly, the terminal computers 12 of the subsequent addresses are connected to the terminals OUT and IN of the adjacent base computers 12 in order by the wiring 141. That is, the wiring 141 and the wiring 141 a are wiring extending from the island computer 11, and the wiring 141 b branched from the middle is connected to the communication interface 122 of each computer 12. In the present embodiment, each of the wirings 141, 141a, and 141b is composed of two wirings, but is shown as one wiring for convenience of illustration.

  Further, as illustrated in the figure, first, a wiring 142 comes out from the output port of the CPU 111 of the island computer 11 via the inverter 113, and the wiring 142 is provided inside the base computer 12 having the address “01”. The input port of the CPU 121 is entered via the inverter 123. Next, a wiring 142 comes out from the output port of the CPU 121 of the base computer 12 via an inverter (output unit) 124, and the wiring 142 is inside the base computer 12 at the address “02”. Similarly, the terminal computers 12 of the subsequent addresses are connected to the terminals OUT and the terminals IN of the adjacent base computers 12 in order by the wiring 142. That is, the wiring 142 serially connects the island computer 11 and the plurality of computer computers 12, and input / output of address signals to be described later is performed through the wiring 142. In the present embodiment, the wiring 142 is composed of the same wiring and the wiring grounded by the island computer 11 and each computer 12, but is shown as one wiring for convenience of illustration. ing.

  In the present embodiment, the wiring 141 and the wiring 142 outside the island computer 11 and the base computer 12 constitute a set of wirings 14. For example, the administrator or the like connects the island computer 11 and the terminal IN of the base computer 12 with the wiring 14, and connects the terminal OUT of the same computer 12 and the terminal IN of the next stage computer 12 with the wiring 14. Thereafter, the connection of the communication system 10 is completed by connecting the terminal OUT and the terminal IN of the adjacent computer bases 12 with the wiring 14.

  The address setting operation by the communication system 10 having the above-described configuration will be described with reference to FIGS. FIG. 2 is a flowchart showing an example of the address setting processing procedure of the computer 12 of this embodiment. FIG. 3 is a flowchart showing an example of the switching procedure of the address setting process and the communication process of the stand computer 12 of this embodiment. FIG. 4 is a schematic diagram illustrating an example of an address signal input to the stand computer 12 and an address signal output from the stand computer 12 according to the present embodiment.

  First, the island computer 11 outputs the address signal of FIG. 4B to the next stage computer 12 of the island computer 12 through the wiring 142. In the example shown in the figure, the address signal has a start signal, a pulse signal, and an end signal. Here, the start signal is a signal that falls from the Hi state and goes into the Lo state for a predetermined time ts (for example, 16 milliseconds). The end signal is a signal that rises from the Lo state and is in the Hi state for a predetermined time te (for example, 16 milliseconds). The pulse signal is a signal that switches from the Hi state to the Lo state in units of the reference time Δt (for example, 8 milliseconds) shown in FIG. 4 between the start signal and the end signal. In the example of FIG. 4B, the number of changes of the pulse signal is 1 (P1). The predetermined times ts and te and the reference time Δt described above are set according to the performance of the CPU 121 and the like in order to reliably decode the address signal.

  Next, the next stage computer 12 of the island computer 11 determines whether or not a start signal is detected as illustrated in FIG. 2 (S100). Hereinafter, for convenience of explanation, the processing procedure when the base computer 12 receives the address signal of FIG. 4B from the island computer 11 will be described. Further, the processing of each step illustrated in FIG. 2 is executed using, for example, the reference time Δt in FIG. 4 as time increments.

  As described above, when it is determined that the start signal that is in the Lo state for a predetermined time ts is detected after falling from the Hi state (S100: YES), the stand computer 12 resets the count value N of the counter 128 to 0. (S101), the process of step S100 is executed again.

  Since the next signal after the start signal is a pulse signal, in step S100 again, the stand computer 12 determines whether or not a pulse signal has been detected via step S100: NO (S102).

  As described above, when it is determined that the pulse signal that switches from the Hi state to the Lo state in units of the reference time Δt is detected, the stand computer 12 increments the count value N of the counter 128 by +1 (S103), and the process of step S100 Run again.

  Since the number of changes in the pulse signal in FIG. 4B is only one (that is, there is no second change), in step S100, the stand computer 12 goes through step S100: NO and again. In step S102, it is determined whether or not an end signal is detected via step S102: NO (S104).

  As described above, when it is determined that an end signal that has been in the Hi state for a predetermined time te or more after rising from the Lo state is detected (S104: YES), the stand computer 12 determines whether the count value N of the counter 128 is greater than zero. Is determined (S105).

  Since the number of changes in the pulse signal in FIG. 4B is one (N = 1), the computer 12 determines that N is greater than 0 (S104: YES), and the address of itself (own station) "01" is set and stored in the RAM 126 (S106), and "02" obtained by adding 1 (predetermined value) to "01" is set as the address of the next stage computer 12 (next station). The address signal shown in FIG. 4C indicating this is transmitted to the next stage computer 12 (S107), and the process of step S100 is executed again. In the example of FIG. 4C, the number of changes of the pulse signal included in the address signal is two (P1, P2).

  Step S105: The process of NO is, for example, a process for an address signal whose pulse signal is noise. In this case, the address setting is not performed for both the own station and the next station.

  Thereafter, the base computer 12 that has received the address signal indicating the address “02” from the front base computer 12 sets “02” as its own address according to the procedure illustrated in FIG. At the same time, “03” obtained by adding 1 (predetermined value) to “02” is set as the address of the next stage computer 12, and an address signal indicating this is transmitted to the next stage computer 12. By repeating this sequentially, each of the plurality of computer systems 12 is set with an address in the connection order starting from the address of the computer computer 12 adjacent to the island computer 11.

  As illustrated in FIG. 3, each computer 12 determines whether an address has been set by the address setting process described above after power-on (S200). When it is determined that the address has already been set (S200: YES), the base computer 12 executes normal communication processing for exchanging operation information and the like (S201), and when it is determined that the address has not yet been set. (S200: NO), the process of S200 is executed again without executing the communication process. Here, the cause of step S200: NO includes, for example, disconnection of the wiring 142, stop of the island computer 11, and the like.

  The communication system 10 according to this embodiment includes at least a plurality of terminal devices (for example, the computer 12) to which unique addresses are set, and terminals that identify the addresses of the plurality of terminal devices and communicate with the plurality of terminal devices. A plurality of terminal devices, each having a decoding unit that decodes an address signal input from the terminal management device or the preceding terminal device, and an address obtained from the decoding unit. It is only necessary to have a setting unit that is set in the terminal device and an output unit that outputs an address signal indicating an address different from the address set in its own terminal device to the terminal device in the next stage. That is, the communication system 10 is not limited to the communication system on the game island, and may be a communication system including a plurality of slave units and a master unit having a clear physical positional relationship, for example. Further, the address of each terminal device is not limited to a number. In short, any address may be used as long as it is different for each terminal device. However, in this case, the terminal management apparatus needs to have a predetermined configuration for recognizing the address set in this way.

  According to this communication system 10, different addresses are automatically set for each of a plurality of terminal devices in the order of connection of the terminal devices, starting from the address of the address signal output from the terminal management device. . As a result, the cost can be reduced to the extent that it is not necessary to mount the aforementioned address setting switch 927 or the like on each terminal device, and the setting is reliable and easy because no human system is involved in the address setting. .

  Further, in the communication system 10 described above, the output unit outputs an address signal indicating an address obtained by adding a predetermined value to the value of the address set in the terminal device of its own, to the terminal device of the next stage. That is, the address of each terminal device is not limited to a serial number such as “01”, “02”, “03”, and for example, “01”, “03”, “07”, etc. The predetermined value to be added is not 1 and may be different for each address. However, in this case, the terminal management apparatus needs to have a predetermined configuration for recognizing the address set in this way.

  According to the communication system 10, since the address is number information whose value increases in the order of connection of a plurality of terminal devices, the structure of data representing each address can be simplified. This leads to a reduction in the capacity of the RAM 126 for storing addresses, for example, leading to cost reduction.

  In the communication system 10 described above, the address signal has a number of pulse signals corresponding to the value of the address, and the decoding unit outputs an address obtained based on the number of changes of the pulse signal to the setting unit, The output unit outputs an address signal having a number of pulse signals corresponding to the address value obtained by adding a predetermined value to the address value to the terminal device at the next stage.

  According to the communication system 10, the address can be reliably set by determining the value of the address based on the number of changes of the pulse signal.

  The above-described embodiments of the present invention are intended to facilitate understanding of the present invention, and are not intended to limit the present invention. The present invention can be changed and improved without departing from the gist thereof, and equivalents thereof are also included in the present invention.

1 Hall computer 9, 10, 90 Communication system 11, 91 Island computer 12, 92 Computer 13, 93 Game table 14, 94, 141, 141a, 141b, 142 Wiring 111, 121, 921 CPU 112, 122, 129 Communication interface 113, 123, 124 Inverter 125 ROM
126 RAM 127 Timer 128 Counter 922, 923 Line 924 Power supply side line 926 Ground side line 925 Pull-up resistor 927 Address setting switch

Claims (3)

A plurality of terminal devices set with unique addresses; and a terminal management device that identifies addresses of the plurality of terminal devices and communicates with the plurality of terminal devices,
Each of the plurality of terminal devices is a decoding unit that decodes an address signal input from the terminal management device or the preceding terminal device, and a setting unit that sets an address obtained from the decoding unit in its own terminal device, An output unit that outputs an address signal indicating an address different from an address set in the terminal device to the terminal device in the next stage. 2. The output unit according to claim 1, wherein the output unit outputs an address signal indicating an address obtained by adding a predetermined value to a value of an address set in the terminal device of the terminal device, to the terminal device of the next stage. Communications system. The address signal has a number of pulse signals corresponding to the value of the address,
The decoding unit outputs the address obtained based on the number of changes in the pulse signal to the setting unit,
3. The output unit according to claim 2, wherein the output unit outputs an address signal having a number of pulse signals corresponding to an address value obtained by adding a predetermined value to the address value to the terminal device at the next stage. Communications system.

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