CN106980587A - A kind of universal input output timing processor and sequential input and output control method - Google Patents
A kind of universal input output timing processor and sequential input and output control method Download PDFInfo
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Classifications
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
- G06F13/38—Information transfer, e.g. on bus
- G06F13/40—Bus structure
- G06F13/4004—Coupling between buses
- G06F13/4027—Coupling between buses using bus bridges
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
- G06F13/38—Information transfer, e.g. on bus
- G06F13/42—Bus transfer protocol, e.g. handshake; Synchronisation
- G06F13/4204—Bus transfer protocol, e.g. handshake; Synchronisation on a parallel bus
- G06F13/4221—Bus transfer protocol, e.g. handshake; Synchronisation on a parallel bus being an input/output bus, e.g. ISA bus, EISA bus, PCI bus, SCSI bus
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
- G06F13/38—Information transfer, e.g. on bus
- G06F13/42—Bus transfer protocol, e.g. handshake; Synchronisation
- G06F13/4282—Bus transfer protocol, e.g. handshake; Synchronisation on a serial bus, e.g. I2C bus, SPI bus
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- Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
- Y02D—CLIMATE CHANGE MITIGATION TECHNOLOGIES IN INFORMATION AND COMMUNICATION TECHNOLOGIES [ICT], I.E. INFORMATION AND COMMUNICATION TECHNOLOGIES AIMING AT THE REDUCTION OF THEIR OWN ENERGY USE
- Y02D10/00—Energy efficient computing, e.g. low power processors, power management or thermal management
Abstract
The present invention relates to a kind of universal input output timing processor and sequential input and output control method, occur counter, sequential RAM memory, serioparallel exchange controller by EBI bridge, processor register file, SECO state machine, sequential to constitute, the processor register file includes multiple sequence control register groups.The beneficial effects of the invention are as follows：Realize a kind of general, that is, support the requirement of various digital port input and output timing variations, tackle various digital interface protocols complicated and changeable；Reduce the chip R＆D cycle；Power consumption is lower.
Description
Technical field
The present invention relates to processor technical field, specifically a kind of universal input output timing processor and sequential are defeated
Enter output control method.
Background technology
In existing chip, if to realize various digital interfaces, its controller just must be internally added.For example
SPI interface is realized, SPI controller is just must be added to, UART interface is added, just must be added to UART controller, to be realized pair
The outer SRAM of piece read and write access just must be added to SRAM controller.But these chips are in the applied field of different users there
Scape is simultaneously differed.Some clients do not need SPI, but chip is integrated with；And some clients need XXX interfaces, but chip does not have
Have integrated；Some clients need 8 road PWM interfaces, and chip is only integrated with 2 tunnels.Integrated chip client unwanted interface,
Cause cost performance to decline, it is not necessary to power consumption can also increase.And often design a kind of interface can be more complicated, extend chip and grind
In the cycle produced, also cause cost increase.The addition of multiplex roles is crossed simultaneously, causes chip design complicated, and leak excessively, occurs
Error probability increase.
The content of the invention
Not enough for above-mentioned prior art, the present invention provides a kind of universal input output timing processor.
A kind of universal input output timing processor and sequential input and output control method that the present invention is provided be by with
What lower technical scheme was realized：
A kind of universal input output timing processor, by EBI bridge, processor register file, SECO state machine, when
Counter, sequential RAM memory, serioparallel exchange controller composition occur for sequence, and the processor register file includes multiple sequences
Control register group, wherein：
The EBI bridge connects processor register file, sequential RAM memory respectively, and EBI bridge is received from bus
CPU various orders pass to each register, serve the effect of a command format conversion；
The processor register file connects SECO state machine, and processor register file is used for the processing number for keeping in processor
According to；
Counter occurs for SECO state machine connection sequential, SECO state machine by fetching controller, decoder, hold
Row device is constituted, and fetching device is used to read control routine, and decoder is used to code analysis and translates into actuator being easy to perform control
Code, actuator be used for coordinate counter specific implementation control；
Counter connection sequential RAM memory occurs for the sequential；
Sequential RAM memory connects serioparallel exchange controller group, and sequential RAM memory stores the control routine of each sequence, side
Be easy to the reading of sequential state machines and serioparallel exchange controller, the serioparallel exchange controller is used to complete bit width conversion, from when
Sequence RAM memory reads data, is then fed sequentially on the pin specified；
In the sequence control register group, 1 sequence control of each sequence control register group correspondence.
The serioparallel exchange controller is two-way, can read data from being currently set on the pin of input, be written to
The specified location of memory.
A kind of sequential input and output control method, by the way of chip pin exchanges data with RAM, in the control of controller
Under system, when being set as output, data output is read from RAM to chip pin；When being set as input, read from chip pin
Access evidence is written in RAM.There are two RAM, 1 RAM in Fig. 2（Data RAM）The data of middle storage input and output sequence.When defeated
The data in RAM are write into chip pin when going out.The data that chip pin is read when input write RAM.Another 1 RAM（Direction
Control RAM）Store the input and output set direction control sequence of sequence.Under the control of the controller with sequence generation successively
The input and output set direction register of input write-in chip pin in reading RAM, control chip input and output direction, also together
When according to direction controlling data RAM be currently reading or write-in；
One or more sequences are stored in RAM, when synchronization only has 1 sequence running or without sequence in fortune
OK；Each sequence correspond in 1 sequence control register group, group at least provided with 4 registers, using baud rate register control
Make the speed of this sequence；
Sequence first address register deposits the beginning address that this sequence is deposited in RAM, and tail address register deposits this sequence
The end address deposited in RAM；Control register indicates the attribute of this sequence.
Common properties have：
1st, direction flexibility is controlled.The direction of this sequence can be controlled as described above using 1 special RAM storage
System, such flexibility is higher, can occur switching direction at any time with sequence.But it can also indicate that this sequence is defeated by this attribute
Enter, or simply export, or input and output are supported simultaneously.Simply enter or export if indicated, then direction controlling RAM is at this
Sequence will not be read when occurring.
2nd, serioparallel exchange is set.Described above is that one kind is set without serioparallel exchange.1 RAM, 1 reading or write-in can
To be 1 byte（8）, 2 bytes（16）Or 4 bytes（32）Etc.（It is described herein by taking 1 byte as an example）, every
1 pin of correspondence chip.But the also a kind setting with serioparallel exchange, the data for being exactly 1 RAM all correspond to 1 pin,
, it is necessary to which the data that each RAM is read are converted into bit stream by parallel-to-serial during write-in pin, be sequentially sent to chip 1 draws
Pin；When reading pin, by the data on pin by serial conversion into parallel data, then RAM is write.When needing to be gone here and there and turned
When changing, if the direction controlling of sequence is provided by RAM, then the data read in direction controlling RAM also to carry out from parallel to
Serial conversion.And if being provided by the control register of this sequence, then need not.
3rd, sequence entry condition is controlled.1 controller can have several groups of sequence control register groups, to support multiple sequences
Occur.The entry condition of each sequence includes：
（1）, when there is rising edge in specified chip pin；
（2）, when there is trailing edge in specified chip pin；
（3）, when there is rising edge or trailing edge in specified chip pin；
（4）, when specified chip pin be equal to 0 when；
（5）, when specified chip pin be equal to 1 when；
（6）, when input and output sequential processing device receives other cpu command requirements and started；
（7）, when specified other input and output sequential processing devices（There can be multiple input and output sequential processing devices in 1 chip）
Some sequence start, concurrently start；
（8）, start when some specified the sequence ends；
4th, big small end control.Indicate the high position or low level first sent in serial transmission in byte.
The beneficial effects of the invention are as follows：
1st, realize a kind of general, that is, support the requirement of various digital port input and output timing variations, tackle complicated and changeable each
Plant digital interface protocol；
2nd, each port need to only support 1 universal input output timing processor, reduce the chip R＆D cycle；
3rd, power consumption is lower；
4th, it can be applied in the various chips with input and output digital interface.It can also be incited somebody to action in application process according to application scenarios
Sequential processing device classifies to be simplified.For example, the sequential processing device on some ports only supports serial input（Read a certain draw
Numerical value on pin, which is gone here and there, to be turned and writes RAM into byte data）Or output（By RAM word joint number according to and turn string and be output to a certain draw
Pin）；Sequential processing device on some ports only supports parallel input（For example, reading the data on 8 pins simultaneously, 1 is used as
Byte writes RAM）Or output（For example, 1 byte parallel is read from RAM is output to 8 pins）, without serioparallel exchange；
Sequential processing device on some ports supports parallel output, and parallel input etc. is not supported.These are provided to according to actual feelings
The category division that condition simplifies design and made.
Brief description of the drawings
Fig. 1 is universal input output timing processor structure schematic diagram；
Fig. 2 is a kind of sequential input and output control method schematic diagram；
Fig. 3 is that serioparallel exchange sets schematic diagram.
Embodiment
Technical scheme will be clearly and completely described by embodiment below, it is clear that described reality
Apply a part of embodiment that example is only the present invention, rather than whole embodiments.Based on the embodiment in the present invention, this area skill
The every other embodiment that art personnel are obtained under the premise of creative work is not made, belongs to the model that the present invention is protected
Enclose.
Literary Chinese and English abbreviation lexical or textual analysis：CPU：Central processor unit；GPIO：Universal input and output port；MUX：Multichannel is selected
Select device；IIC：IC bus；UART：Universal asynchronous receiving-transmitting transmitter；PWM：Pulse width modulation；RAM：Arbitrary access is deposited
Reservoir；SPI：Serial Peripheral Interface (SPI)；Peripheral hardware IP：In the Reusable Design Methodology of integrated circuit, IP kernel, full name intellectual property
Core（English：intellectual property core）, it is logic unit, chip design to refer to one party is provided, form
Reusable module.
Embodiment 1：
A kind of universal input output timing processor as shown in Figure 1, by EBI bridge, processor register file, sequential control
State machine processed, counter, sequential RAM memory, serioparallel exchange controller composition.
The various orders that EBI bridge is used to receive CPU from bus pass to each register.Serve a life
The effect for making form change.
Several sequence control register groups are included inside processor register file（Each register group 1 sequence of correspondence
Control）, the processing data for keeping in processor.Sequence first address register have recorded the visit in memory of sequence to be occurred
The initial address asked, sequence tail address register have recorded the end address in memory of sequence to be occurred.Sequence control
Register has direction flexibility control, serioparallel exchange, entry condition, big small end control, sequence length control, frequency control
System, position enable etc..
Sequence length controls the length and sequence frequency that occur sequence.Its sequence length maximum is limited to storage
The size of device, the capacity of sequential memory is determined according to application scenarios and the system specification.Capacity is bigger, sequence length maximum
It is bigger.Sequence length minimum value is 1.1 sequence of storage incessantly is also noted that in memory, multiple sequences can be stored.
Can also be by the generation sequencing and number of times of each sequence of programme-control.
The frequency of each sequence is from only occurring 1 time to many times（Continue ceaselessly to occur）.Each sequence starts
Condition have：1st, directly initiated by CPU controls；2nd, start or start simultaneously with some sequence when some the sequence ends；3、
When occurring the rising edge specified, trailing edge, edge on input pin（Rising edge or trailing edge）, opened when during equal to 0 or equal to 1
Dynamic, these conditions will enter control register by CPU configured in advance.The operation speed of sequence will occur for the control of sequence rate register
Degree, i.e., each how many clock cycle of bit occupancy.Each sequence is supported to set different speed.
Position, which is enabled, determines it is which pin participates in the generation of this sequence actually.
It is central controller that state of a control machine, which occurs, for sequence, each step that determining sequence occurs, and is embodied.Therewith
The counter of cooperation plays a part of the auxiliary control of timing.Sequence occurs state of a control machine and is made up of 3 controllers.Fetching device
For reading control routine, decoder is used for code analysis and translates into the code that actuator is easy to perform control.And actuator
For coordinating counter specific implementation control.
Sequential RAM memory stores the control routine of each sequence, is convenient to sequential state machines and serioparallel exchange controller
Reading.CPU can access this RAM memory as accessing common RAM memory, so when sequential processor does not work
When, this RAM memory can be used as general memory for CPU.
Because the bit wide of the data read from memory and the data of write-in is fixed, and each sequence is acted on
Pin number it is different, the numbering of pin is also different.Such as sequence A controls 4 pins, is pin 0,1,2,3 respectively；Sequence
Row B controls 8 pins, is pin 0,1,5,6,10,11,12,13 respectively.So needing serioparallel exchange controller to complete this
Individual conversion operation.Serioparallel exchange controller is used to complete bit width conversion, is determined by central controller, and number is read from memory
According to being then fed sequentially on the pin of formulation.Serioparallel exchange controller is two-way simultaneously, from the pin for being currently set to input
Upper reading data, are written to the specified location of memory.
Embodiment 2
A kind of sequential input and output control method as shown in Figure 2, by the way of chip pin exchanges data with RAM, in control
Under the control of device processed, when being set as output, data output is read from RAM to chip pin；When being set as input, from core
Piece pin reads data and is written in RAM.There are two RAM, 1 RAM in Fig. 2（Data RAM）Middle storage input and output sequence
Data.The data in RAM are write into chip pin when output.The data that chip pin is read when input write RAM.Another 1
Individual RAM（Direction controlling RAM）Store the input and output set direction control sequence of sequence.Under the control of the controller with sequence
The input and output set direction register for the input write-in chip pin being successively read in RAM, control chip input is defeated
Outgoing direction, also while being currently reading or write-in according to direction controlling data RAM；
One or more sequences are stored in RAM, when synchronization only has 1 sequence running or without sequence in fortune
OK；Each sequence correspond in 1 sequence control register group, group at least provided with 4 registers, using baud rate register control
Make the speed of this sequence；
Sequence first address register deposits the beginning address that this sequence is deposited in RAM, and tail address register deposits this sequence
The end address deposited in RAM；Control register indicates the attribute of this sequence.
Common properties have：
1st, direction flexibility is controlled.The direction of this sequence can be controlled as described above using 1 special RAM storage
System, such flexibility is higher, can occur switching direction at any time with sequence.But it can also indicate that this sequence is defeated by this attribute
Enter, or simply export, or input and output are supported simultaneously.Simply enter or export if indicated, then direction controlling RAM is at this
Sequence will not be read when occurring.
2nd, serioparallel exchange is set.Described above is that one kind is set without serioparallel exchange.1 RAM, 1 reading or write-in can
To be 1 byte（8）, 2 bytes（16）Or 4 bytes（32）Etc.（It is described herein by taking 1 byte as an example）, every
1 pin of correspondence chip.But the also a kind setting with serioparallel exchange, the data for being exactly 1 RAM all correspond to 1 pin,
, it is necessary to which the data that each RAM is read are converted into bit stream by parallel-to-serial during write-in pin, be sequentially sent to chip 1 draws
Pin；When reading pin, by the data on pin by serial conversion into parallel data, then RAM is write.When needing to be gone here and there and turned
When changing, if as shown in figure 3, the direction controlling of sequence is provided by RAM, then the data read in direction controlling RAM will also be entered
Go from parallel-to-serial conversion.And if being provided by the control register of this sequence, then need not.
3rd, sequence entry condition is controlled.1 controller can have several groups of sequence control register groups, to support multiple sequences
Occur.The entry condition of each sequence includes：
（1）, when there is rising edge in specified chip pin；
（2）, when there is trailing edge in specified chip pin；
（3）, when there is rising edge or trailing edge in specified chip pin；
（4）, when specified chip pin be equal to 0 when；
（5）, when specified chip pin be equal to 1 when；
（6）, when input and output sequential processing device receives other cpu command requirements and started；
（7）, when specified other input and output sequential processing devices（There can be multiple input and output sequential processing devices in 1 chip）
Some sequence start, concurrently start；
（8）, start when some specified the sequence ends；
4th, big small end control.Indicate the high position or low level first sent in serial transmission in byte.
Embodiment described above only represents embodiments of the present invention, and it describes more specific and detailed, but can not manage
Solve as limitation of the scope of the invention.It should be pointed out that for those skilled in the art, not departing from structure of the present invention
On the premise of think of, various modifications and improvements can be made, these belong to the scope of the present invention.
Claims (7)
1. a kind of universal input output timing processor, it is characterised in that：By EBI bridge, processor register file, sequential
Counter, sequential RAM memory, serioparallel exchange controller composition, the processor register file occur for state of a control machine, sequential
Comprising multiple sequence control register groups, wherein：
The EBI bridge connects processor register file, sequential RAM memory respectively, and EBI bridge is received from bus
CPU various orders pass to each register, serve the effect of a command format conversion；
The processor register file connects SECO state machine, and processor register file is used for the processing number for keeping in processor
According to；
Counter occurs for SECO state machine connection sequential, SECO state machine by fetching controller, decoder, hold
Row device is constituted, and fetching device is used to read control routine, and decoder is used to code analysis and translates into actuator being easy to perform control
Code, actuator be used for coordinate counter specific implementation control；
Counter connection sequential RAM memory occurs for the sequential；
Sequential RAM memory connects serioparallel exchange controller group, and sequential RAM memory stores the control routine of each sequence, side
Be easy to the reading of sequential state machines and serioparallel exchange controller, the serioparallel exchange controller is used to complete bit width conversion, from when
Sequence RAM memory reads data, is then fed sequentially on the pin specified.
2. a kind of universal input output timing processor according to claim 1, it is characterised in that：The sequence control is posted
In storage group, 1 sequence control of each sequence control register group correspondence.
3. a kind of universal input output timing processor according to claim 1, it is characterised in that：The serioparallel exchange control
Device processed is two-way, can read data from being currently set on the pin of input, be written to the specified location of memory.
4. a kind of sequential input and output control method, it is characterised in that：By the way of chip pin exchanges data with RAM,
Under the control of controller, when being set as output, data output is read from RAM to chip pin；When being set as input, from
Chip pin reads data and is written in RAM；
One or more sequences are stored in RAM, when synchronization only has 1 sequence running or without sequence in fortune
OK；Each sequence correspond in 1 sequence control register group, group at least provided with 4 registers, using baud rate register control
Make the speed of this sequence；
Sequence first address register deposits the beginning address that this sequence is deposited in RAM, and tail address register deposits this sequence
The end address deposited in RAM；Control register indicates the attribute of this sequence.
5. a kind of sequential input and output control method according to claim 4, it is characterised in that：The RAM includes data
RAM and direction controlling RAM.
6. a kind of sequential input and output control method according to claim 4, it is characterised in that the attribute includes：
A, direction flexibility control, the direction of this sequence can be controlled using 1 special RAM storage, can be occurred with sequence
Switching direction at any time；Also it can indicate that this sequence is simply entered by this attribute, or simply export, or input and output are supported simultaneously；
Simply enter or export if indicated, then direction controlling RAM will not be read when this sequence occurs；
B, serioparallel exchange are set, it is necessary to when carrying out serioparallel exchange, if the direction controlling of sequence is provided by RAM, then controlled in direction
The data read in RAM processed will be also carried out from parallel-to-serial conversion；If being provided by the control register of this sequence, then
Need not；
C, the control of sequence entry condition；1 controller can have several groups of sequence control register groups, to support multiple sequences to send out
It is raw；
D, the control of big small end, indicate the high position or low level first sent in serial transmission in byte.
7. a kind of sequential input and output control method according to claim 6, it is characterised in that the sequence entry condition
In control, the entry condition of each sequence includes：
A, when there is rising edge in specified chip pin；
B, when there is trailing edge in specified chip pin；
C, when there is rising edge or trailing edge in specified chip pin；
D, when specified chip pin be equal to 0 when；
E, when specified chip pin be equal to 1 when；
F, when input and output sequential processing device receives other cpu command requirements and started；
G, when specified other input and output sequential processing devices（There can be multiple input and output sequential processing devices in 1 chip）'s
Some sequence starts, and concurrently starts；
H, start when some specified the sequence ends.
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| CN201710335729.8A CN106980587B (en) | 2017-05-12 | 2017-05-12 | General input/output time sequence processor and time sequence input/output control method |
| CN202310732544.6A CN117033279A (en) | 2017-05-12 | 2017-05-12 | Time sequence input and output control method |
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Cited By (4)
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| CN109062857A (en) * | 2018-08-14 | 2018-12-21 | 苏州硅岛信息科技有限公司 | A kind of new type of messages controller and its communication means that can be communicated between realization of High Speed multiprocessor |
| CN109669894A (en) * | 2018-12-21 | 2019-04-23 | 天津国芯科技有限公司 | A kind of universal asynchronous receiving-transmitting device reducing chip package pin |
| CN110245096A (en) * | 2019-06-24 | 2019-09-17 | 苏州硅岛信息科技有限公司 | A method of realizing that processor is directly connected to extension computing module |
| CN112255944A (en) * | 2020-10-16 | 2021-01-22 | 同济大学 | Driving structure of multi-path parallel ultrasonic sensor |
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| CN201418086Y (en) * | 2007-12-05 | 2010-03-03 | 中国科学院空间科学与应用研究中心 | Data communication protocol controller used for satellite-borne equipment |
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| CN109669894A (en) * | 2018-12-21 | 2019-04-23 | 天津国芯科技有限公司 | A kind of universal asynchronous receiving-transmitting device reducing chip package pin |
| CN110245096A (en) * | 2019-06-24 | 2019-09-17 | 苏州硅岛信息科技有限公司 | A method of realizing that processor is directly connected to extension computing module |
| CN112255944A (en) * | 2020-10-16 | 2021-01-22 | 同济大学 | Driving structure of multi-path parallel ultrasonic sensor |
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| CN117033279A (en) | 2023-11-10 |
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