CN110618950B - Asynchronous FIFO read-write control circuit and method, readable storage medium and terminal - Google Patents

Asynchronous FIFO read-write control circuit and method, readable storage medium and terminal Download PDF

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CN110618950B
CN110618950B CN201810628386.9A CN201810628386A CN110618950B CN 110618950 B CN110618950 B CN 110618950B CN 201810628386 A CN201810628386 A CN 201810628386A CN 110618950 B CN110618950 B CN 110618950B
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clock
read
write
fifo memory
link
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CN110618950A (en
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王鹏
吴涛
高鹏
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Shanghai Information Technology Research Center
Shanghai Advanced Research Institute of CAS
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Shanghai Advanced Research Institute of CAS
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    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/14—Handling requests for interconnection or transfer
    • G06F13/16—Handling requests for interconnection or transfer for access to memory bus
    • G06F13/1605—Handling requests for interconnection or transfer for access to memory bus based on arbitration
    • G06F13/161—Handling requests for interconnection or transfer for access to memory bus based on arbitration with latency improvement
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/14—Handling requests for interconnection or transfer
    • G06F13/16—Handling requests for interconnection or transfer for access to memory bus
    • G06F13/1668—Details of memory controller

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Abstract

The invention provides an asynchronous FIFO read-write control circuit, the control circuit at least includes: the FIFO memory, a first clock, a second clock, a first logic link and a second logic link; a write clock domain of the FIFO memory is accessed into a first clock, a read clock domain of the FIFO memory is accessed into a second clock, a write pointer interface of the FIFO memory is connected with a first end of a first logic link, a second end of the first logic link is connected with a trigger signal end, a read pointer interface of the FIFO memory is connected with a first end of a second logic link, and a second end of the second logic link is connected with the trigger signal end; the first logic link is composed of a first number of trigger chains, the second logic link is composed of a second number of trigger chains, and the first logic link is at least two triggers more than the second logic link. By applying the embodiment of the invention, the time delay time difference between the read pointer and the write pointer can be accurately controlled, and the minimization of the read-write time delay of the FIFO memory is realized.

Description

Asynchronous FIFO read-write control circuit and method, readable storage medium and terminal
Technical Field
The invention relates to the technical field of reading and writing control of FIFO memories, in particular to an asynchronous FIFO reading and writing control circuit and method, a readable storage medium and a terminal.
Background
FIFO (First Input First Output, first in First out queue) according to the in-order execution method, the First entered instruction is completed and retired First, then the second instruction is executed. FIFO is widely used in large scale integrated circuit design as a first-in first-out data memory, generally used as a buffer. The FIFO memory is divided into a read clock area and a write clock area on a physical area, and is used for reading data and writing data, respectively.
As shown in fig. 1, when an asynchronous FIFO is used for high-speed digital design, if a high level signal is received, in one path, a write pointer is triggered to move by the high level, and a write operation is performed in a write clock region of the FIFO memory; in the other path, the high-level signal is input into a metastable state eliminating circuit consisting of 4 triggers and generates a read enabling high-level signal, after two logic processes, the read enabling high-level signal triggers a read pointer to move through the triggers, and data reading is carried out in a read clock domain.
In the read clock domain, the read pointer address and the write pointer address need to be compared and judged to obtain a state value of the read null signal, so as to determine the next operation of read enabling. In this determination process, the write pointer signal needs to be processed across clock domains. When the data cache facing the high-speed code stream is processed, the clock domain crossing operation is realized, and the sending of the read enabling instruction is completed, and as the data needs to be delayed through each trigger after passing through at least 4 triggers for metastable state elimination and one trigger for a read enabling signal, at least 5-6 clock cycles are needed. At this time, the data is written into the FIFO multiple address spaces, and the read pointer is ready to read the data,
therefore, in the prior art, the access process of the asynchronous FIFO memory correspondingly generates a delay of at least 5-6 clock cycles because other logic functional blocks in the circuit occupy some delay. In applications with high low latency requirements, the use of a conventional asynchronous FIFO generally results in an excessive overall latency of the system, which cannot meet the design requirements.
Disclosure of Invention
In view of the above-mentioned shortcomings of the prior art, an object of the present invention is to provide an asynchronous FIFO read-write control circuit and method, a readable storage medium and a terminal, which are used to solve the problem of the prior art that the delay time between the write operation and the read operation of the FIFO memory is too long.
To achieve the above and other related objects, the present invention provides an asynchronous FIFO read/write control circuit, comprising: the system comprises a FIFO memory, a first clock, a second clock, a first logic link and a second logic link; the write clock domain of the FIFO memory is accessed to the first clock, the read clock domain of the FIFO memory is accessed to the second clock, the write pointer interface of the FIFO memory is connected with the first end of the first logic link, the second end of the first logic link is connected with the trigger signal end, the read pointer interface of the FIFO memory is connected with the first end of the second logic link, and the second end of the second logic link is connected with the trigger signal end; the first logical link is composed of a first number of series of flip-flops, the second logical link is composed of a second number of series of flip-flops, and the first logical link is at least two more flip-flops than the second logical link.
In a preferred embodiment of the present invention, the first clock and the second clock are clock signals having the same frequency and different phases.
In a preferred embodiment of the present invention, the first number is at least 3 and the second number is at least 5.
In a preferred embodiment of the present invention, the delay time of each flip-flop on the first logical link is a first clock cycle; the delay time of each flip-flop on the second logical link is one second clock cycle.
In a preferred embodiment of the present invention, the phase difference between the first clock and the second clock is 90 °.
In addition, the invention also discloses an asynchronous FIFO read-write control method, which comprises the following steps: receiving a trigger signal; judging whether the trigger signal is a high level signal; if yes, delaying the trigger signal through a trigger on a first logic link to generate a write enable high level signal, and sending the write enable high level signal to a write pointer interface of the FIFO memory, wherein the delay time of the trigger on the first logic link is first time; the trigger signal is processed by a trigger on a second logic link across clock domains to generate a read enable high level signal, and the read enable high level signal is sent to a read pointer interface of the FIFO memory, wherein the delay time of the trigger on the second logic link is a second time; and under the condition that the first delay time is less than the second delay time, performing data writing operation through a writing pointer of the FIFO memory and a first clock signal, and performing data reading operation through a reading pointer of the FIFO memory and a second clock signal.
In a preferred embodiment of the present invention, the first clock and the second clock are clock signals having the same frequency and different phases.
In a preferred embodiment of the present invention, the delay time of each flip-flop on the first logical link is a first clock cycle; the delay time of each flip-flop on the second logical link is one second clock cycle.
Furthermore, the present invention provides a readable storage medium, on which a computer program is stored, which when executed by a processor implements the steps of the asynchronous FIFO read-write control method according to any one of the claims.
And the terminal comprises a processor memory, wherein the memory stores program instructions, and the processor runs the program instructions to realize the steps in any asynchronous FIFO read-write control method.
As described above, the asynchronous FIFO read-write control circuit and method, the readable storage medium, and the terminal according to the present invention have the following beneficial effects:
(1) The punishment is carried out through the trigger signal, the time delay difference between the read pointer and the write pointer can be accurately controlled, and the minimization of the read-write delay of the FIFO memory is realized.
(2) The FIFO memory read enable is controlled by the output end of the second logic link and is not controlled by a read empty signal output by the FIFO memory any longer, and the FIFO memory always has no overflow.
Drawings
FIG. 1 is a schematic diagram of a FIFO read/write control circuit in the prior art
FIG. 2 is a schematic diagram of an asynchronous FIFO read/write control circuit according to the present invention.
FIG. 3 is a schematic diagram of an embodiment of an asynchronous FIFO read/write control circuit according to the present invention.
Fig. 4 is a timing diagram of fig. 3.
FIG. 5 is a schematic diagram of another embodiment of the asynchronous FIFO read/write control circuit according to the invention.
FIG. 6 is a flow chart of the asynchronous FIFO read/write control method according to the present invention.
Description of the element reference numerals
1 FIFO memory
2. First clock
3. Second clock
4. First logical link
5. Second logical link
6. Trigger signal terminal
S501-S505 steps
Detailed Description
The embodiments of the present invention are described below with reference to specific embodiments, and other advantages and effects of the present invention will be easily understood by those skilled in the art from the disclosure of the present specification. The invention is capable of other and different embodiments and of being practiced or of being carried out in various ways, and its several details are capable of modification in various respects, all without departing from the spirit and scope of the present invention.
It should be noted that the drawings provided in the present embodiment are only for illustrating the basic idea of the present invention, and the components related to the present invention are only shown in the drawings rather than drawn according to the number, shape and size of the components in actual implementation, and the type, quantity and proportion of the components in actual implementation may be changed freely, and the layout of the components may be more complicated.
Referring to fig. 2, a schematic circuit connection diagram of an asynchronous FIFO read-write control circuit provided in an embodiment of the present invention is shown, where the control circuit at least includes: the FIFO memory comprises a FIFO memory 1, a first clock 2, a second clock 3, a first logic link 4 and a second logic link 5; a write clock domain of the FIFO memory 1 is accessed to a first clock 2, a read clock domain of the FIFO memory 1 is accessed to a second clock 3, a write pointer interface of the FIFO memory 1 is connected with a first end of a first logic link 4, a second end of the first logic link 4 is connected with a trigger signal end 6, a read pointer interface of the FIFO memory 1 is connected with a first end of a second logic link 5, and a second end of the second logic link 5 is connected with the trigger signal end 6; the first logical link 4 is composed of a first number of series of flip-flops, the second logical link 5 is composed of a second number of series of flip-flops, and the first logical link 4 is at least one flip-flop more than the second logical link 5.
It should be noted that the depth of the FIFO memory is the number of storage cells in the FIFO memory, and the depth is generally set to be larger than the actual use depth. The mentioned overflow means that the FIFO memory is "read empty" or "written full", and "read empty" means that the reading pointer pointing unit is the same as the writing pointer pointing unit, the data in the memory cell is read empty, and the FIFO "read empty" signal outputs logic "1"; "full" means that the FIFO internal memory cell is full, and the "full" indication signal outputs a logic "1".
As will be understood by those skilled in the art, the trigger signal terminal 6 is connected to the second terminals of the first and second logical links 4 and 5, and is configured to send a trigger signal to the first and second logical links 4 and 5, and when the trigger signal is at a high level, the triggers in the first and second logical links 4 and 5 can be triggered, so that the high levels output by the triggers are sequentially transmitted. That is, when the trigger signal is at a high level, taking the first clock as an example, the delay time of each flip-flop is one first clock cycle.
The trigger signal is delayed for several cycles after passing through the first logic link 4 and the second logic link 5 and then is input into the FIFO memory, the write operation is performed when the write pointer interface of the memory receives a high level signal, the read operation is performed according to the second clock when the read pointer interface of the memory receives a high level signal, and the write operation is performed according to the first clock.
In order to further ensure that the FIFO memory is prevented from being empty, the FIFO memory is read after being written, that is, the write pointer interface of the FIFO memory receives a high level signal earlier than the read pointer interface, so the delay time in the second logical link 5 is longer than the delay time in the first logical link 4, and the first logical link has at least one more flip-flop than the second logical link due to the relationship between the delay time and the number of flip-flops. Therefore, the high level signal received by the reading pointer interface is synchronous with the second clock, the high level signal received by the writing pointer interface is synchronous with the first clock, and the FIFO memory reads and then writes. The read and write delay time is related to the number difference of the triggers on the first logical link and the second logical link, and as long as the number difference of the triggers is fixed, the delay of the write pointer and the read pointer of the FIFO memory is fixed. Therefore, by applying the embodiment of the invention, the time delay difference between the read pointer and the write pointer can be accurately controlled by punishing through the trigger signal, and the minimization of the read-write time delay of the FIFO memory is realized.
In the write clock domain, the write pointer is controlled by the write enable signal, moves among the storage units of the FIFO memory, and continuously writes the storage data; and in the read clock domain, the read enable controls the read pointer to move among the FIFO memory cells to realize the read operation of the data. Typically the read enable valid/reset control command is given by a read empty indication signal. The "read empty" signal determines whether to output logic 0 or logic 1 by comparing the physical addresses of the write pointer and the read pointer, and the comparison between the two is realized by firstly performing clock domain crossing operation on the write pointer and synchronizing the write pointer to the read clock domain. Generally, in low-speed design, 2-3 stages of flip-flops are needed to be added for synchronous processing of single-bit signals, but in high-speed digital design, 4 stages of flip-flops are needed to be added to eliminate metastable states to complete synchronous processing of signals. If the comparison logic is added to output a read empty signal and then trigger the read enable to execute the read pointer operation, the write pointer has passed through at least 5-6 memory cells, resulting in a delay of 5-6 clock cycles.
It can be understood that a certain phase difference is generated after the frequencies provided by the same crystal oscillator pass through different clock paths, and the phase difference is not fixed. In order to eliminate the influence of such clock instability on the logic, for example, a phase difference between the first clock and the second clock is 90 °, or a phase difference between the first clock and the second clock is 30 °, or a phase difference between the first clock and the second clock is 60 °, or a phase difference between the first clock and the second clock is 120 °, or a phase difference between the first clock and the second clock is 180 °, as long as there is a stable phase difference, and the phase difference is not specifically limited in the embodiment of the present invention.
It can be understood that when the number of the flip-flops is large, the caused delay is too long, and in the embodiment of the present invention, it is only required to ensure that the time when the read pointer receives the high level is later than the time when the write pointer receives the high level, that is, a certain delay time is generated, and the delay time may be within a certain range.
For example, in fig. 3, the number of the flip-flops on the first logical link is 3, the number of the flip-flops on the second logical link is 5, and a specific timing diagram is shown in fig. 4, after passing through the first two flip-flops on the first logical link, the write enable signal is at a high level (after the trigger signal is at the high level, the two flip-flops correspond to the write enable signal that rises to the high level after passing through the rising edges of the two first clocks), the read-write enable signal passes through the flip-flops, then the high level signal is sent to the first logical module, and after passing through the first logical module, the read-write enable signal is sent to the write pointer interface of the FIFO memory, and the pointer jump is performed to implement the write operation. And after the first four triggers on the second logic link, the read enable signal is at a high level (after the trigger signal is at the high level, the four triggers correspondingly rise to the high level after the rising edges of four second clocks), and the read enable signal sends the high level signal to the second logic module after passing through the triggers and sends the high level signal to a read pointer interface of the FIFO memory after passing through the second logic module to perform pointer jump to realize read operation.
Another implementation of the present invention is shown in fig. 5, wherein the first logical link includes 5 flip-flops, and the second logical link includes 7 flip-flops. Correspondingly, the trigger signal is synchronized in a read clock domain, the cross-clock operation is realized through 4 triggers of the first logic link, meanwhile, the second logic link ensures the minimum delay between FIFO reading and writing, and the functions realized by the invention are also realized.
In addition, as shown in fig. 6, the present invention also discloses an asynchronous FIFO read-write control method, which comprises:
s501, receiving a trigger signal;
s502, judging whether the trigger signal is a high level signal or not, and if so, executing S103.
S503, generating a write enable high level signal after delaying through a trigger on the first logic link, and sending the write enable high level signal to a write pointer interface of the FIFO memory, wherein the delay time of the trigger on the first logic link is the first time.
S504, generating a read enable high level signal after delaying through a trigger on a second logic link, and sending the read enable high level signal to a write pointer interface of the FIFO memory, wherein the delay time of the trigger on the second logic link is a second time.
And S505, under the condition that whether the first delay time is less than the second delay time, performing data writing operation through a writing pointer and a first clock signal of the FIFO memory, and performing data reading operation through a reading pointer and a second clock signal of the FIFO memory.
In an implementation manner of the present invention, the first clock and the second clock are clock signals with the same frequency and different phases.
In an implementation manner of the present invention, a delay time of each flip-flop on the first logical link is a first clock cycle; the delay time of each flip-flop on the second logical link is one second clock cycle.
The steps of the method provided in fig. 5 of the present invention are implemented based on the asynchronous FIFO read-write control circuit of fig. 1, and the write enable high level signal described in the embodiment of the present invention is a high level state of the write enable signal, and the specific process is not described herein with reference to fig. 1.
In addition, the invention also discloses a readable storage medium, wherein a computer program is stored on the readable storage medium, and the computer program realizes the steps of any asynchronous FIFO read-write control method when being executed by a processor.
And the terminal comprises a processor memory, wherein the memory stores program instructions, and the processor runs the program instructions to realize the steps in any asynchronous FIFO read-write control method.
In summary, according to the asynchronous FIFO read-write control circuit and method, the readable storage medium, and the terminal of the present invention, the level of the write pointer interface and the level of the read pointer interface from the first logical link and the second logical link to the FIFO memory are controlled by one trigger end, and the delay time of the write operation and the read operation is determined by the number difference of the triggers on the first logical link and the second logical link, so that the delay time difference between the read pointer and the write pointer can be accurately controlled, and the minimization of the read-write delay of the FIFO memory is achieved. Therefore, the invention effectively overcomes various defects in the prior art and has high industrial utilization value.
The foregoing embodiments are merely illustrative of the principles and utilities of the present invention and are not intended to limit the invention. Any person skilled in the art can modify or change the above-mentioned embodiments without departing from the spirit and scope of the present invention. Accordingly, it is intended that all equivalent modifications or changes which can be made by those skilled in the art without departing from the spirit and technical spirit of the present invention be covered by the claims of the present invention.

Claims (9)

1. An asynchronous FIFO read-write control circuit, characterized in that the control circuit comprises at least: the FIFO memory, a first clock, a second clock, a first logic link and a second logic link;
the write clock domain of the FIFO memory is accessed to the first clock, the read clock domain of the FIFO memory is accessed to the second clock, the write pointer interface of the FIFO memory is connected with the first end of the first logic link, the second end of the first logic link is connected with the trigger signal end, the read pointer interface of the FIFO memory is connected with the first end of the second logic link, and the second end of the second logic link is connected with the trigger signal end;
the first logical link is composed of a first number of series of flip-flops, the second logical link is composed of a second number of series of flip-flops, and the first logical link is at least two more flip-flops than the second logical link.
2. The asynchronous FIFO read-write control circuit of claim 1, wherein the first clock and the second clock are clock signals of the same frequency and different phases.
3. The asynchronous FIFO read-write control circuit of claim 1 or 2, wherein the first number is at least 3 and the second number is at least 5.
4. The asynchronous FIFO read-write control circuit of claim 1, wherein the latency time of each flip-flop on the first logical link is one first clock cycle; the delay time of each flip-flop on the second logical link is one second clock cycle.
5. An asynchronous FIFO read-write control method, characterized in that the control method comprises:
receiving a trigger signal;
judging whether the trigger signal is a high level signal;
if yes, delaying the trigger signal through a trigger on a first logic link to generate a write enable high level signal, and sending the write enable high level signal to a write pointer interface of the FIFO memory, wherein the delay time of the trigger on the first logic link is first time;
the trigger signal is processed through a trigger on a second logic link across a clock domain to generate a read enabling high level signal, and the read enabling high level signal is sent to a read pointer interface of the FIFO memory, wherein the delay time of the trigger on the second logic link is a second time;
and under the condition that the first time is less than the second time, performing data writing operation through a writing pointer of the FIFO memory and a first clock signal, and performing data reading operation through a reading pointer of the FIFO memory and a second clock signal.
6. The asynchronous FIFO read-write control method of claim 5, wherein the first clock and the second clock are clock signals of the same frequency and different phases.
7. The asynchronous FIFO read-write control method of claim 5, wherein the latency time of each flip-flop on the first logical link is a first clock cycle; the delay time of each flip-flop on the second logical link is one second clock cycle.
8. A readable storage medium, having stored thereon a computer program, characterized in that the program, when being executed by a processor, implements the steps of the asynchronous FIFO read-write control method according to any one of claims 6 to 7.
9. A terminal comprising a processor memory having stored thereon program instructions, characterized in that: the processor executes the program instructions to implement the steps in the asynchronous FIFO read-write control method according to any one of claims 6 to 7.
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Citations (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US7752506B1 (en) * 2003-09-16 2010-07-06 Cypress Semiconductor Corporation FIFO memory error circuit and method
CN103095289A (en) * 2011-11-08 2013-05-08 澜起科技（上海）有限公司 Signal delay control circuit
CN203870424U (en) * 2014-05-21 2014-10-08 北京宇航系统工程研究所 Clock domain-crossing asynchronous FIFO control logic circuit
CN104484011A (en) * 2014-11-25 2015-04-01 上海高性能集成电路设计中心 Distributive control and double-clock asynchronous sending and receiving module and FIFO (First In First Out) device
CN104793918A (en) * 2014-01-17 2015-07-22 阿尔特拉公司 Deterministic fifo buffer
CN107220023A (en) * 2017-06-29 2017-09-29 中国电子科技集团公司第五十八研究所 A kind of embedded configurable FIFO memory

Family Cites Families (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP1396786A1 (en) * 2002-09-03 2004-03-10 STMicroelectronics Limited Bridge circuit for use in retiming in a semiconductor integrated circuit

Patent Citations (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US7752506B1 (en) * 2003-09-16 2010-07-06 Cypress Semiconductor Corporation FIFO memory error circuit and method
CN103095289A (en) * 2011-11-08 2013-05-08 澜起科技（上海）有限公司 Signal delay control circuit
CN104793918A (en) * 2014-01-17 2015-07-22 阿尔特拉公司 Deterministic fifo buffer
CN203870424U (en) * 2014-05-21 2014-10-08 北京宇航系统工程研究所 Clock domain-crossing asynchronous FIFO control logic circuit
CN104484011A (en) * 2014-11-25 2015-04-01 上海高性能集成电路设计中心 Distributive control and double-clock asynchronous sending and receiving module and FIFO (First In First Out) device
CN107220023A (en) * 2017-06-29 2017-09-29 中国电子科技集团公司第五十八研究所 A kind of embedded configurable FIFO memory

Non-Patent Citations (2)

* Cited by examiner, † Cited by third party
Title
一种低功耗异步FIFO存储器的设计;张海勇等;《现代电子技术》;20080915(第18期);全文 *
基于多时钟域的异步FIFO设计;杨青山等;《中国集成电路》;20070905(第09期);全文 *

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