CN111949582B

CN111949582B - Pointer synchronization device and method, asynchronous FIFO circuit and processor system

Info

Publication number: CN111949582B
Application number: CN202010866691.9A
Authority: CN
Inventors: 陈佰儒; 刘勋
Original assignee: Haiguang Information Technology Co Ltd
Current assignee: Haiguang Information Technology Co Ltd
Priority date: 2020-08-25
Filing date: 2020-08-25
Publication date: 2022-01-18
Anticipated expiration: 2040-08-25
Also published as: CN111949582A

Abstract

The application provides a pointer synchronization device and method, an asynchronous FIFO circuit and a processor system, comprising a memory, a write index logic module and a read index logic module, wherein the clock cycle of the write index logic module is a fast clock cycle, and the clock cycle of the read index logic module is a slow clock cycle; the write index logic module determines write time according to the fast clock period and the slow clock period, and writes a first pointer into the memory at the write time; the index reading logic module reads a first pointer from a memory according to a slow clock cycle; wherein, the writing time satisfies: so that the time difference from the same first pointer being written to the memory to being read from the memory is the first target delay time. The determination of the write time makes the time difference from being written to being read of the same first pointer be the first target delay time, which is shorter than the delay time in the prior art, so that the requirement of low delay of data transmission of a high-performance processor can be met.

Description

Pointer synchronization device and method, asynchronous FIFO circuit and processor system

Technical Field

The present application relates to the field of computers, and in particular, to a pointer synchronization apparatus and method, an asynchronous FIFO circuit, and a processor system.

Background

When data transmission is carried out between different clock domains in the digital integrated circuit, the data transmission needs to be processed by a clock domain crossing circuit. The clock domain crossing circuit is usually an asynchronous FIFO circuit.

In the prior art, when an asynchronous FIFO circuit performs clock domain crossing synchronization of pointers, usually, a plurality of Digital Flip-flops (DFFs) delay a delay time of a number of clock cycles of the DFFs by a clock cycle of a target clock domain, so as to achieve synchronization of the pointers.

The prior art has long delay time when the pointer is synchronized across clock domains, and cannot meet the requirement of a high-performance processor on low delay of data transmission.

Disclosure of Invention

An object of the embodiments of the present invention is to provide a pointer synchronization apparatus and method, an asynchronous FIFO circuit, and a processor system, so as to solve the problem of long delay time when a pointer crosses a clock domain for synchronization in the prior art.

In a first aspect, an embodiment of the present application provides a pointer synchronization apparatus, configured to implement synchronization of pointers between different clock domains, where each clock domain includes a fast clock domain and a slow clock domain, and the apparatus includes a memory, a write index logic module, and a read index logic module, where the memory is connected to the write index logic module and the read index logic module respectively, a clock cycle of the write index logic module is the same as a fast clock cycle of the fast clock domain, and a clock cycle of the read index logic module is the same as a slow clock cycle of the slow clock domain; the write index logic module is used for determining write time according to the fast clock cycle and the slow clock cycle and writing a first pointer into the memory at the write time; the read index logic module is used for reading a first pointer from the memory according to the slow clock period; wherein the writing time satisfies: such that the time difference between the same first pointer being written to memory by the write index logic and being read from memory by the read index logic is a first target latency.

In the foregoing embodiment, the clock cycle in which the write index logic module is located is the same as the slow clock cycle of the slow clock domain, the clock cycle in which the read index logic module is located is the same as the fast clock cycle of the fast clock domain, the read index logic module determines the write time at which the first pointer is written into the memory according to the fast clock cycle and the slow clock cycle, and the write index logic module reads the first pointer from the memory according to the slow clock cycle, where the determination of the write time may make the time difference between writing and reading of the same first pointer be the first target delay time, and the first target delay time is the delay time set by the user and may be shorter than the delay time for synchronization of pointers across clock domains in the prior art, for example, two fast clock cycles, so that the requirement of a high-performance processor for low delay of data transmission may be met.

In one possible design, the write index logic is to: determining a write time according to the fast clock cycle and the slow clock cycle, and writing a first pointer into the memory at the write time, specifically including: every time a fast clock period passes, reducing a counting value by a numerical value corresponding to the fast clock period, wherein the initial value of the counting value is a numerical value corresponding to the slow clock period; and when the count value is smaller than 0, writing a first pointer into the memory, and increasing the count value by a numerical value corresponding to the slow clock period, wherein the time corresponding to the count value smaller than 0 is the writing time.

In the above embodiment, the write index logic module may calculate a time when the first pointer is written into the memory by using the cycle time of the fast clock cycle and the cycle time of the slow clock cycle, and with the slow clock cycle as an initial value of the count value, every time a fast clock cycle passes, the count value is subtracted from the value corresponding to the fast clock cycle until the count value is less than 0, and the first pointer is written into the memory, and the current count value is added to the value corresponding to the slow clock cycle to recover the state where the count value is greater than or equal to 0. By the mode, the speeds of writing in the pointer data and reading out the pointer data are similar on the premise that the writing index logic module and the reading index logic module work in respective clock cycles, and the delay time is more convenient to calculate under the condition of similar speeds.

In one possible design, the memory includes a predetermined number of memory spaces, each of the memory spaces being used for storing a pointer; the writing index logic module is specifically configured to sequentially write a first pointer into one of a preset number of storage spaces in the memory according to the writing time; and the index reading logic module is used for sequentially reading a first pointer from one of the preset number of storage spaces in the memory according to the slow clock period.

In the above embodiment, the memory may include a plurality of memory spaces, and the write index logic module may sequentially write data according to the order of the cache addresses of the memory spaces when writing the data; when the read index logic module reads data from the storage space, the data can also be read sequentially according to the sequence of the cache addresses of the storage space, and the plurality of storage spaces enable the memory to cache a plurality of first pointers at the same time, so that the synchronization efficiency of the first pointers in the clock domain crossing synchronization process is further improved.

In one possible design, each of the memory spaces has a corresponding cache address, and the apparatus further includes: the system comprises a write index beacon module, a read index beacon module and a phase tracking module, wherein the write index beacon module and the read index beacon module are connected with the phase tracking module, and the phase tracking module is also connected with a write index logic module; the write index beacon module is used for generating a write beacon signal and enabling the write beacon signal to be overturned when the write index logic module writes a first pointer into a storage space corresponding to a target cache address for N times; the index reading beacon module is used for generating a beacon reading signal and enabling the beacon reading signal to be overturned when the index reading logic module reads the first pointer from the storage space corresponding to the target cache address for N times; the phase tracking module is used for generating a write index control signal according to the write beacon signal and the read beacon signal and sending the write index control signal to the write index logic module so that the write index logic module adjusts the write time.

In the above embodiment, the write index beacon module may perform inversion of a write beacon signal once when the write index logic module writes the first pointer to the target buffer address every N times, so as to generate a write beacon signal with an inversion point at the target buffer address; the index reading beacon module may perform one inversion of the read beacon signal every time the index reading logic module reads the first pointer from the storage space corresponding to the same target cache address for N times, so as to generate the read beacon signal with the inversion point at the same target cache address. The write beacon signal and the read beacon signal can be both transmitted to the phase tracking module, so that the phase tracking module generates a write index control signal according to the time difference between the write beacon signal and the read beacon signal, and the write index control signal can be sent to the write index logic module, so that the write index logic module can adjust the write time. The write time is adjusted by the feedback of the read beacon signal and the write beacon signal, so that the time difference from the writing to the reading of the same first pointer is stably maintained at the first target delay time, and the stability of the first target delay time is improved.

In one possible design, the device further includes M first registers, where the M first registers are sequentially connected between the read index beacon module and the phase tracking module, and are used to delay a read beacon signal generated by the read index beacon module by M fast clock cycles and then transmit the delayed read beacon signal to the phase tracking module, so as to synchronize the read beacon signal from a slow clock domain to a fast clock domain.

In the above embodiment, in order to make the read beacon signal and the write beacon signal be compared together, the read beacon signal may be synchronized through the M first registers, and the read beacon signal is synchronized from the slow clock domain to the fast clock domain after delaying by M fast clock cycles.

In one possible design, the phase tracking module is configured to generate a write index control signal according to the write beacon signal and the read beacon signal, and specifically includes: delaying the write mark signal by the sum of M fast clock periods and the first target delay time to obtain a delayed write mark signal; comparing the delayed write beacon signal with the read beacon signal delayed by M fast clock periods; if the turning point of the waveform of the delayed write beacon signal is earlier than the turning point of the waveform of the read beacon signal delayed by M fast clock periods, generating a WrEearly signal, wherein the WrEearly signal is a mark signal which represents that the time of writing the first pointer is earlier than the expected time; and if the turning point of the waveform of the delayed write beacon signal is later than the turning point of the waveform of the read beacon signal delayed by M fast clock periods, generating a Wrlate signal, wherein the WrEearly signal is a mark signal which represents that the time of writing the first pointer is later than the expected time.

In the above embodiment, after receiving the read beacon signal delayed by M fast clock cycles, the phase tracking module delays the write beacon signal by M fast clock cycles, delays the write beacon signal by the first target delay time, compares the write beacon signal with the read beacon signal by the first target delay time, and if waveforms of the write beacon signal and the read beacon signal are aligned, it indicates that a time difference between writing and reading of the same first pointer is exactly the first target delay time; if the turning point of the waveform of the delayed write beacon signal is earlier than that of the waveform of the delayed read beacon signal, the writing time is earlier, and a corresponding write index control signal WrEearly signal is generated; if the inversion point of the delayed write beacon signal is later than the inversion point of the delayed read beacon signal, it indicates that the write time is later, and a corresponding write index control signal WrLate is generated.

In one possible design, the write index logic module is further to: when the count value is greater than or equal to 0, if a WrEearly signal is received, when the count value is supposed to be decreased by the value corresponding to the fast clock period, the action of decreasing the value corresponding to the fast clock period is not carried out; when the counting value is greater than or equal to 0, if a Wrlate signal is received, reducing the values corresponding to the two fast clock cycles when the counting value is supposed to be reduced by the value corresponding to the fast clock cycle; and when the count value is less than 0, adding the count value to a numerical value corresponding to the slow clock period so as to recover the state that the count value is greater than or equal to 0.

In the above embodiment, when the count value is greater than or equal to 0 and the WrEarly signal is received, and the count value should be decreased by the value corresponding to the fast clock cycle, the write index logic module does not perform an operation of decreasing the value corresponding to the fast clock cycle, so as to prolong the time when the count value reaches the state less than 0, and further postpone the write time of writing the first pointer into the memory; when the count value is greater than or equal to 0 and the WrLate signal is received, the write index logic module additionally reduces the value corresponding to one fast clock cycle when the count value is reduced by the value corresponding to the fast clock cycle, so that the time for the count value to reach a state less than 0 is shortened, and the write-in time for writing the first pointer into the memory is advanced; and when the count value is less than 0, adding the count value to a value corresponding to the slow clock period so as to restore the count value to be greater than or equal to 0. The writing index logic module adjusts the writing time according to different writing index control signals, so that the time difference from writing to reading of the same first pointer is kept stable, and the first target delay time is kept.

In one possible design, the apparatus further includes: the circuit comprises a first conversion module, a second conversion module and L second registers, wherein the L second registers are sequentially connected between the first conversion module and the second conversion module; the first conversion module is used for converting a second pointer running in a slow clock domain from a binary code to a Gray code; the L second registers are used for delaying the Gray code representing the second pointer by L fast clock cycles and then sending the Gray code representing the second pointer to the second conversion module; the second conversion module is configured to convert the gray code delayed by L fast clock cycles into a binary code, and output the binary code converted by the gray code to complete synchronization of the second pointer, where the L fast clock cycles are delay times of synchronization of the second pointer.

In the above embodiment, for the second pointer synchronized from the slow clock domain to the fast clock domain, since the target clock domain is the fast clock domain, the synchronization between the two can be realized by L second registers, and the synchronization across the clock domains of the second pointer still has a low delay time under the condition of keeping the implementation structure simple.

In a second aspect, an embodiment of the present application provides a pointer synchronization apparatus, configured to implement synchronization of pointers in different clock domains, where each clock domain includes a fast clock domain and a slow clock domain, the apparatus includes a buffer, a slow-write index logic module, and a fast-read index logic module, where the buffer is connected to the slow-write index logic module and the fast-read index logic module, respectively, a clock cycle of the slow-write index logic module is the same as a slow clock cycle of the slow clock domain, and a clock cycle of the fast-read index logic module is the same as a fast clock cycle of the fast clock domain; the slow writing index logic module is used for writing a second pointer into the buffer according to the slow clock period; the fast reading index logic module is used for determining reading time according to the fast clock period and the slow clock period and reading a second pointer from the buffer at the reading time; wherein the readout timing satisfies: and the time difference from the time when the same second pointer is written into the buffer by the slow-writing index logic module to the time when the same second pointer is read out of the buffer by the fast-reading index logic module is a second target delay time.

In the above embodiment, the determination of the reading time may make the time difference between the writing and reading of the second pointer be the second target delay time, which is the delay time set by the user, and may be shorter than the delay time of the pointer synchronization across the clock domain in the prior art, for example, two fast clock cycles, so that the requirement of the high-performance processor for low delay of data transmission may be satisfied.

In one possible design, the fast read index logic module is configured to determine a read time according to the fast clock cycle and the slow clock cycle, and read a second pointer from the buffer at the read time, and specifically includes: every time a fast clock period passes, reducing the accumulated value by a numerical value corresponding to the fast clock period, wherein the initial value of the accumulated value is a numerical value corresponding to the slow clock period; and when the accumulated value is smaller than 0, reading a second pointer from the buffer, and increasing the accumulated value by a value corresponding to the slow clock period, wherein the time corresponding to the accumulated value smaller than 0 is the reading time.

In the above embodiment, the slow-write index logic module and the fast-read index logic module may work in respective clock cycles, and the speeds of the write pointer and the read pointer are similar, so that it is more convenient to calculate the delay time in the case of similar speeds.

In one possible design, the buffer includes a preset number of buffer spaces, and each buffer space is used for storing a pointer; the slow-write index logic module is specifically configured to sequentially write a second pointer into one of a preset number of cache spaces in the cache according to the slow clock cycle; and the index reading logic module is used for sequentially reading a second pointer from one of the preset number of cache spaces in the cache according to the reading time.

In the above embodiment, the plurality of buffer spaces enable the buffer to buffer the plurality of second pointers at the same time, thereby further improving the synchronization efficiency when the first pointer is synchronized across clock domains.

In one possible design, each of the cache spaces has a corresponding cache address, and the apparatus further includes: the system comprises a slow-write index beacon module, a fast-read index beacon module and a read phase tracking module, wherein the slow-write index beacon module and the fast-read index beacon module are connected with the read phase tracking module, and the read phase tracking module is also connected with the fast-read index logic module; the slow writing index beacon module is used for generating a slow writing beacon signal and enabling the slow writing beacon signal to be overturned when the slow writing index logic module writes a second pointer into a cache space corresponding to a target cache address for N times; the fast reading index beacon module is used for generating a fast reading beacon signal and enabling the fast reading beacon signal to turn over when the fast reading index logic module reads a second pointer for N times from a cache space corresponding to the target cache address; the read phase tracking module is used for generating a read index control signal according to the slow write beacon signal and the fast read beacon signal and sending the read index control signal to the fast read index logic module so that the fast read index logic module adjusts the read time.

In the above-described embodiment, the read timing is adjusted by the feedback of the fast read beacon signal and the slow write beacon signal, so that the time difference between the time when the same second pointer is read and written is stably maintained at the second target delay time, thereby improving the stability of the second target delay time.

In a possible design, the device further comprises M digital flip-flops, which are sequentially connected between the slow write index beacon module and the read phase tracking module, and are configured to delay a slow write beacon signal generated by the slow write index beacon module by M fast clock cycles and then transmit the delayed slow write beacon signal to the read phase tracking module, so as to synchronize the slow write beacon signal from a slow clock domain to a fast clock domain.

In the above embodiment, in order to make the slow write beacon signal and the fast read beacon signal be compared together, the synchronization of the slow write beacon signal may be implemented by M digital flip-flops, and the slow write beacon signal is synchronized from the slow clock domain to the fast clock domain after being delayed by M fast clock cycles.

In one possible design, the read phase tracking module is configured to generate a read index control signal according to the slow write beacon signal and the fast read beacon signal, and specifically includes: delaying the fast reading beacon signal by the difference between M fast clock cycles and the second target delay time to obtain a delayed fast reading beacon signal; comparing the delayed fast reading beacon signal with the delayed slow writing beacon signal after M fast clock periods; if the turning point of the waveform of the delayed fast reading beacon signal is earlier than the turning point of the waveform of the slow writing beacon signal after delaying M fast clock periods, an RdEearly signal is generated, and the RdEearly signal is a mark signal representing that the time for reading the second pointer is earlier than the expected time; and if the turning point of the waveform of the delayed fast reading beacon signal is later than the turning point of the waveform of the slow writing beacon signal after delaying the M fast clock cycles, generating an Rdlate signal, wherein the Rdlate signal is a mark signal which represents that the time for reading the second pointer is later than the expected time.

In one possible design, the fast-read index logic module is further to: when the accumulated value is greater than or equal to 0, if an RdEearly signal is received, when the accumulated value is supposed to reduce the value corresponding to the fast clock period, the action of reducing the value corresponding to the fast clock period is not carried out; when the accumulated value is greater than or equal to 0, if an Rdlate signal is received, reducing the values corresponding to the two fast clock cycles when the accumulated value is supposed to reduce the value corresponding to the fast clock cycle; and when the accumulated value is less than 0, adding the accumulated value to a value corresponding to the slow clock period to restore the state that the accumulated value is greater than or equal to 0.

In the above embodiment, the fast-read index logic module adjusts the read time according to different read index control signals, so as to keep the time difference between the writing and the reading of the same second pointer stable and maintain the second target delay time.

In a third aspect, an embodiment of the present application provides an asynchronous FIFO circuit, including the first aspect, any possible design of the first aspect, the second aspect, and the pointer synchronization apparatus in any possible design of the second aspect, a write pointer logic module, a write full flag logic module, a read pointer logic module, a read empty flag logic module, and a dual port memory; the write pointer logic module is used for sending a write pointer to the pointer synchronization device so that the pointer synchronization device can obtain a synchronized write pointer and send the synchronized write pointer to the read empty mark logic module; the read empty flag logic module is used for judging whether the data in the dual-port memory is read empty according to the synchronized write pointer and read pointer; the read pointer logic module is used for sending the read pointer to the pointer synchronization device so that the pointer synchronization device can obtain a synchronized read pointer and send the synchronized read pointer to the write full flag logic module; the write-full flag logic module is used for judging whether the dual-port memory is fully written with data according to the synchronized read pointer and write pointer; the dual-port memory is used for receiving the write pointer of the write pointer logic module and writing data to the position pointed by the write pointer; and the read pointer logic module is also used for receiving the read pointer of the read pointer logic module and reading data from the position pointed by the read pointer.

In the foregoing embodiment, whether the write pointer is synchronized to the clock domain where the read pointer is located, or the read pointer is synchronized to the clock domain where the write pointer is located, may be performed by the pointer synchronization apparatus in any possible design of the first aspect and the first aspect, and after the clock domain crossing synchronization is completed, the full flag logic module performs the determination on whether the write pointer is full, and the empty flag logic module performs the determination on whether the read pointer is empty. The pointer synchronization device shortens the time difference from writing to reading of the same pointer, so that the judgment of full writing or empty reading is accelerated, and the working efficiency of hardware is improved.

In a fourth aspect, the present application provides a processor system comprising the asynchronous FIFO circuit of the second aspect, a first electrical component and a second electrical component, the first and second electrical components being in communication through the asynchronous FIFO circuit, the first electrical component operating in a fast clock cycle, the second electrical component operating in a slow clock cycle.

In a fifth aspect, the present application provides a pointer synchronization method, configured to implement synchronization of pointers between different clock domains through a pointer synchronization apparatus, where the clock domains include a fast clock domain and a slow clock domain, the pointer synchronization apparatus includes a memory, a write index logic module, and a read index logic module, where the memory is connected to the write index logic module and the read index logic module respectively, a clock cycle of the write index logic module is the same as a fast clock cycle of the fast clock domain, and a clock cycle of the read index logic module is the same as a slow clock cycle of the slow clock domain; the method comprises the following steps: the write index logic module determines write time according to the fast clock cycle and the slow clock cycle, and writes a first pointer into the memory at the write time; the read index logic module reads a first pointer from the memory according to the slow clock period; wherein the writing time satisfies: such that the time difference between the same first pointer being written to memory by the write index logic and being read from memory by the read index logic is a first target latency.

In one possible design, the determining, by the write index logic module, a write time according to the fast clock cycle and the slow clock cycle, and writing a first pointer to the memory at the write time includes: every time a fast clock period passes, reducing a counting value by a numerical value corresponding to the fast clock period, wherein the initial value of the counting value is a numerical value corresponding to the slow clock period; and when the count value is smaller than 0, writing a first pointer into the memory, and increasing the count value by a numerical value corresponding to the slow clock period, wherein the time corresponding to the count value smaller than 0 is the writing time.

In one possible design, the memory includes a predetermined number of memory spaces, each of the memory spaces being used for storing a pointer; the writing a first pointer to the memory at the write time includes: writing a first pointer into one of a preset number of storage spaces in the memory sequentially at the writing time; the reading the first pointer from the memory according to the slow clock cycle includes: and sequentially reading the first pointer from one of the preset number of storage spaces in the memory according to the slow clock period.

In one possible design, each of the memory spaces has a corresponding cache address, and the pointer synchronization apparatus further includes: the system comprises a write index beacon module, a read index beacon module and a phase tracking module, wherein the write index beacon module and the read index beacon module are connected with the phase tracking module, and the phase tracking module is also connected with a write index logic module; the method further comprises the following steps: the write index beacon module generates a write beacon signal, and when the write index logic module writes a first pointer into a storage space corresponding to a target cache address for N times, the write beacon signal is enabled to be overturned; the index reading beacon module generates a beacon reading signal, and when the index reading logic module reads a first pointer from a storage space corresponding to the target cache address for N times, the beacon reading signal is turned over; and the phase tracking module generates a write index control signal according to the write beacon signal and the read beacon signal and sends the write index control signal to the write index logic module so that the write index logic module adjusts the write time.

In one possible design, the pointer synchronization apparatus further includes: the M first registers are sequentially connected between the read index beacon module and the phase tracking module, and before the phase tracking module generates a write index control signal according to the write beacon signal and the read beacon signal and sends the write index control signal to the write index logic module, the method further comprises: and the M first registers delay the reading beacon signals generated by the reading index beacon module by M fast clock cycles and then transmit the reading beacon signals to the phase tracking module so as to realize the synchronization of the reading beacon signals from a slow clock domain to a fast clock domain.

In one possible design, the phase tracking module generates a write index control signal based on the write beacon signal and the read beacon signal, including: delaying the write mark signal by the sum of M fast clock periods and the first target delay time to obtain a delayed write mark signal; comparing the delayed write beacon signal with the read beacon signal delayed by M fast clock periods; if the turning point of the waveform of the delayed write beacon signal is earlier than the turning point of the waveform of the read beacon signal delayed by M fast clock periods, generating a WrEearly signal, wherein the WrEearly signal is a mark signal which represents that the time of writing the first pointer is earlier than the expected time; and if the turning point of the waveform of the delayed write beacon signal is later than the turning point of the waveform of the read beacon signal delayed by M fast clock periods, generating a Wrlate signal, wherein the WrEearly signal is a mark signal which represents that the time of writing the first pointer is later than the expected time.

In one possible design, the method further includes: when the count value is greater than or equal to 0, if the write index logic module receives a WrEarly signal, the write index logic module does not perform an action of reducing the value corresponding to the fast clock cycle when the count value is supposed to reduce the value corresponding to the fast clock cycle; when the count value is greater than or equal to 0, if the write index logic module receives a WrLate signal, reducing the values corresponding to the two fast clock cycles when the count value is to be reduced by the value corresponding to the fast clock cycle; and when the count value is less than 0, the write index logic module adds the count value to a numerical value corresponding to the slow clock period so as to recover the state that the count value is greater than or equal to 0.

In one possible design, the pointer synchronization apparatus further includes: the circuit comprises a first conversion module, a second conversion module and L second registers, wherein the L second registers are sequentially connected between the first conversion module and the second conversion module; the method further comprises the following steps: the first conversion module converts a second pointer running in a slow clock domain from binary codes to Gray codes; the L second registers delay the Gray code representing the second pointer by L fast clock cycles and then send the Gray code representing the second pointer to the second conversion module; the second conversion module converts the gray code delayed by L fast clock cycles into a binary code, and outputs the binary code converted by the gray code to complete the synchronization of the second pointer, wherein the L fast clock cycles are delay time of the synchronization of the second pointer.

In a sixth aspect, an embodiment of the present application provides a pointer synchronization method, configured to implement synchronization of pointers in different clock domains through a pointer synchronization apparatus, where the clock domains include a fast clock domain and a slow clock domain, the apparatus includes a buffer, a slow-write index logic module, and a fast-read index logic module, where the buffer is connected to the slow-write index logic module and the fast-read index logic module respectively, a clock cycle of the slow-write index logic module is the same as a slow clock cycle of the slow clock domain, and a clock cycle of the fast-read index logic module is the same as a fast clock cycle of the fast clock domain; the method comprises the following steps: the slow writing index logic module writes a second pointer into the buffer according to the slow clock period; the fast reading index logic module determines reading time according to the fast clock period and the slow clock period, and reads a second pointer from the buffer at the reading time; wherein the readout timing satisfies: and the time difference from the time when the same second pointer is written into the buffer by the slow-writing index logic module to the time when the same second pointer is read out of the buffer by the fast-reading index logic module is a second target delay time.

In one possible design, the determining, by the fast-read index logic module, a read time according to the fast clock cycle and the slow clock cycle, and reading a second pointer from the buffer at the read time includes: every time a fast clock period passes, reducing the accumulated value by a numerical value corresponding to the fast clock period, wherein the initial value of the accumulated value is a numerical value corresponding to the slow clock period; and when the accumulated value is smaller than 0, reading a second pointer from the buffer, and increasing the accumulated value by a value corresponding to the slow clock period, wherein the time corresponding to the accumulated value smaller than 0 is the reading time.

In one possible design, the buffer includes a preset number of buffer spaces, and each buffer space is used for storing a pointer; the slow-write index logic module writes a second pointer into the buffer according to the slow clock cycle, and specifically includes: the slow writing index logic module writes a second pointer into one cache space in a preset number of cache spaces in the cache in sequence according to the slow clock period; the fast-reading index logic module determines a reading time according to the fast clock cycle and the slow clock cycle, and reads a second pointer from the buffer at the reading time, and the method specifically includes: and the index reading logic module reads the second pointer from one of the preset number of cache spaces in the cache in sequence according to the reading time.

In one possible design, the method further includes: the slow writing index beacon module generates a slow writing beacon signal, and when the slow writing index logic module writes a second pointer into a cache space corresponding to a target cache address for N times, the slow writing beacon signal is turned over; the fast reading index beacon module generates a fast reading beacon signal, and when the fast reading index logic module reads a second pointer from a cache space corresponding to the target cache address for N times, the fast reading beacon signal is turned over; and the reading phase tracking module generates a reading index control signal according to the slow writing beacon signal and the fast reading beacon signal, and sends the reading index control signal to the fast reading index logic module so that the fast reading index logic module adjusts the reading time.

In one possible design, the generating, by the read phase tracking module, a read index control signal according to the slow write beacon signal and the fast read beacon signal specifically includes: delaying the fast reading beacon signal by the difference between M fast clock cycles and the second target delay time to obtain a delayed fast reading beacon signal; comparing the delayed fast reading beacon signal with the delayed slow writing beacon signal after M fast clock periods; if the turning point of the waveform of the delayed fast reading beacon signal is earlier than the turning point of the waveform of the slow writing beacon signal after delaying M fast clock periods, an RdEearly signal is generated, and the RdEearly signal is a mark signal representing that the time for reading the second pointer is earlier than the expected time; and if the turning point of the waveform of the delayed fast reading beacon signal is later than the turning point of the waveform of the slow writing beacon signal after delaying the M fast clock cycles, generating an Rdlate signal, wherein the Rdlate signal is a mark signal which represents that the time for reading the second pointer is later than the expected time.

In one possible design, the method further includes: when the accumulated value is greater than or equal to 0, if the fast reading index logic module receives an RdEearly signal, when the accumulated value is supposed to reduce the value corresponding to the fast clock period, the action of reducing the value corresponding to the fast clock period is not performed; when the accumulated value is greater than or equal to 0, if the fast reading index logic module receives an Rdlate signal, reducing the values corresponding to the two fast clock cycles when the accumulated value is supposed to reduce the value corresponding to the fast clock cycle; and when the accumulated value is less than 0, the fast reading index logic module adds the accumulated value to a numerical value corresponding to the slow clock period so as to recover the state that the accumulated value is greater than or equal to 0.

In order to make the aforementioned and other objects, features and advantages of the present invention comprehensible, preferred embodiments accompanied with figures are described in detail below.

Drawings

In order to more clearly illustrate the technical solutions of the embodiments of the present application, the drawings that are required to be used in the embodiments of the present application will be briefly described below, it should be understood that the following drawings only illustrate some embodiments of the present application and therefore should not be considered as limiting the scope, and that those skilled in the art can also obtain other related drawings based on the drawings without inventive efforts.

Fig. 1 is a schematic block diagram of a pointer synchronization apparatus in the prior art;

fig. 2 is a schematic structural block diagram of a pointer synchronization apparatus provided in an embodiment of the present application;

FIG. 3 shows a waveform diagram for obtaining a write target signal;

FIG. 4 illustrates a waveform diagram of acquiring a read beacon signal;

fig. 5 shows a waveform diagram for acquiring a WrEarly signal;

fig. 6 shows a waveform diagram for acquiring a WrLate signal;

FIG. 7 is a block diagram showing a schematic structure of a write index logic block in the pointer synchronization apparatus;

FIG. 8 is a schematic block diagram illustrating a specific implementation of a pointer synchronization apparatus provided in an embodiment of the present application;

FIG. 9 is a schematic block diagram of an asynchronous FIFO circuit provided in an embodiment of the present application;

FIG. 10 shows a timing diagram for a fast handshake state machine handshaking with a slow handshake state machine;

fig. 11 is a schematic structural block diagram illustrating another specific implementation of a pointer synchronization apparatus provided in an embodiment of the present application;

FIG. 12 shows a waveform diagram for obtaining a slow write target signal;

fig. 13 shows a waveform diagram for acquiring a fast read beacon signal;

fig. 14 shows a waveform diagram for acquiring an RdLate signal;

fig. 15 shows a waveform diagram for acquiring an RdEarly signal;

FIG. 16 is a block diagram showing a schematic structure of a fast-reading index logic module in the pointer synchronization apparatus;

FIG. 17 is a flowchart illustrating a pointer synchronization method according to an embodiment of the present application;

fig. 18 is a flowchart showing a specific step of step S110 in fig. 17;

FIG. 19 is a flowchart illustrating a portion of steps of a pointer synchronization method provided by an embodiment of the present application;

fig. 20 is a flowchart illustrating a specific step of step S230 in fig. 19.

Detailed Description

In the prior art, the synchronization of pointers across clock domains is usually realized by a plurality of DFFs 11, please refer to fig. 1, each DFF 11 includes an input end D, an output end Q, and a CLK end, each CLK end is connected to a clock signal of a target clock domain, and the DFFs 11 are connected in series by the input end D and the output end Q. Referring to fig. 1, an input terminal D of the rightmost DFF 11 in fig. 1 is used for receiving a pointer from an electrical component, an output terminal Q of the rightmost DFF 11 is connected to an input terminal D of the DFF 11 located at the center in fig. 1, an output terminal Q of the DFF 11 located at the center is connected to an input terminal D of the leftmost DFF 11 in fig. 1, and an output terminal Q of the leftmost DFF 11 in fig. 1 is used for sending a pointer to another electrical component.

The input end D receives a pointer, and the output end Q outputs a pointer every time the CLK end receives a trigger signal. The trigger signal may be a waveform-inverted signal of the clock signal, for example, the trigger signal may be a rising edge of the clock signal or a falling edge of the clock signal.

When the clock domain crossing synchronization of the pointers is performed in the above manner, the delay time is the product of the number of DFFs and the clock cycle of the target clock domain, and if the clock domain crossing synchronization is from the fast clock domain to the slow clock domain, that is, the target clock domain is the slow clock domain, the delay time is long.

The embodiment of the application realizes the clock domain crossing synchronization of the pointer by writing the pointer into the memory and reading the pointer from the memory after the first target delay time. The pointer can be read out from the memory according to the slow clock cycle of the slow clock domain, the write-in time of the pointer is determined according to the fast clock cycle and the slow clock cycle of the fast clock domain, the write-in time meets the condition that the time difference from write-in to read-out of the same pointer is the first target delay time, and the first target delay time is shorter than the product of the number of DFFs and the clock cycle of the target clock domain, so that the delay time of pointer synchronization across the clock domains is shortened, and the requirement of a high-performance processor on low delay of data transmission is met.

The technical solutions in the embodiments of the present application will be described below with reference to the drawings in the embodiments of the present application.

Referring to fig. 2, fig. 2 is a schematic structural block diagram of a pointer synchronization apparatus provided in an embodiment of the present application, which can synchronize pointers between different clock domains, where the clock domains include a fast clock domain and a slow clock domain. The pointer synchronization apparatus includes a memory 110, a write index logic module 120, a read index logic module 130, a write index beacon module 140, a read index beacon module 150, and a phase tracking module 160. The write index logic 120 and the read index logic 130 are both connected to the memory 110, the clock cycle of the write index logic 120 is the same as the fast clock cycle of the fast clock domain, and the clock cycle of the read index logic 130 is the same as the slow clock cycle of the slow clock domain.

The write index logic 120 is configured to determine a write time according to the fast clock cycle and the slow clock cycle, and write a first pointer to the memory 110 at the write time. The first pointer may be a write pointer indicating a position where data is written, or a read pointer indicating data is read from a position. The specific type of first pointer should not be construed as limiting the application.

The read index logic 130 is configured to read the first pointer from the memory 110 according to the slow clock cycle.

The above-mentioned write timing satisfies: such that the time difference between the same first pointer being written to memory 110 by the write index logic 120 and read from memory 110 by the read index logic 130 is a first target latency. The first target delay time is a delay time of a first pointer, which is expected by a user, synchronized across a time domain, and the first target delay time may be specifically a time occupied by two fast clock cycles, or may be a delay time of another value. The first target delay time may be other values, such as three fast clock cycles, on the premise that the unstable data can be changed into the stable data, and the specific value of the first target delay time should not be construed as a limitation to the present application.

Alternatively, in a specific embodiment, the writing time may be determined as follows:

every time a fast clock period passes, the counting value is reduced by a value corresponding to the fast clock period;

it is determined whether the count value is less than 0.

If the count value is not less than 0, jumping to the step: every time a fast clock period passes, the counting value is reduced by a value corresponding to the fast clock period;

if the count value is less than 0, a first pointer is written into the memory 110, the count value is increased by a value corresponding to the slow clock period, and then the following steps are performed: and reducing the count value by the value corresponding to the fast clock cycle every time one fast clock cycle passes.

When the count value is smaller than 0, the corresponding time is the write-in time, and the initial value of the count value is a numerical value corresponding to the slow clock period.

If the slow clock period is set to 2.5ns, the fast clock period is set to 1.2ns, and the current value of the count value is the initial value, that is, the value 2.5 corresponding to the slow clock period, then when one fast clock period passes, the count value is decreased by the value 1.2 corresponding to the fast clock period, and the current count value is 2.5-1.2, which is 1.3.

If the current count value 1.3 is not less than 0, the count value is decreased by a value 1.2 corresponding to the fast clock cycle after another fast clock cycle, and the current count value is 1.3-1.2, which is equal to 0.1.

If the current count value 0.1 is not less than 0, the count value is decreased by a value 1.2 corresponding to the fast clock cycle after a fast clock cycle, and the current count value is 0.1-1.2-1.1.

If the current count value-1.1 is smaller than 0, the current time is the write time, a first pointer is written into the memory 110, and the current count value is incremented by the value corresponding to the slow clock cycle, so that the current count value is-1.1 +2.5 — 1.4.

And for the current counting value 1.4, continuously executing the following steps: and reducing the count value by the value corresponding to the fast clock cycle every time one fast clock cycle passes.

When the count value is less than 0, a first pointer is written into the memory 110 because the binary negative number is easy to judge for hardware, and the binary number can be judged to be positive or negative according to the highest bit of the binary number, thereby improving the efficiency of hardware execution.

It should be understood that the time corresponding to the count value being less than 0 may be the writing time, and the time corresponding to the count value being less than or equal to 0 may also be the writing time.

Alternatively, in another specific embodiment, the writing time may be determined as follows: if the value corresponding to the fast clock cycle is P and the value corresponding to the slow clock cycle is i × P, the write index logic module 120 writes a first pointer into the memory 110 every i fast clock cycles, and the write time is: initial time + k × i, where k is a natural number.

The memory 110 includes a predetermined number of memory spaces, each for storing a pointer, each of the memory spaces having a corresponding cache address.

The write index logic module 120 may point to a cache address in a predetermined number of storage spaces at a certain write time, so that the first pointer is written into the storage space corresponding to the cache address; at the next writing time, the next cache addresses of the cache addresses are sequentially pointed to, so that the first pointer is written into the storage space corresponding to the cache address currently pointed to by the write index logic module 120.

The read index logic module 130 may point to a cache address in a preset number of storage spaces after a slow clock cycle elapses, so as to read a first pointer from the storage space corresponding to the cache address; after another slow clock cycle, the next cache address of the cache addresses is sequentially pointed to, so that the first pointer is read from the cache address currently pointed to by the read index logic module 130.

For convenience of description, it is not required to set the predetermined number of storage spaces as 6 storage spaces, and the cache addresses of the 6 storage spaces are 0, 1, 2, 3, 4, and 5, respectively. Then:

the write index logic module 120 may point to a cache address in the 6 storage spaces at a certain write time, and is not set to 2, so that the first pointer is written into the storage space corresponding to the cache address 2; and at the next writing time, sequentially pointing to the cache address 3, so that the first pointer is written into the storage space corresponding to the cache address 3.

After a slow clock cycle elapses, the read index logic module 130 may point to a cache address in 6 storage spaces, which is not set to 4, so as to read the first pointer from the storage space corresponding to the cache address 4; after a further slow clock cycle has elapsed, the buffer addresses 5 are sequentially pointed to, so that the first pointer is read from the buffer address 5.

Referring to fig. 2, the write index beacon module 140 and the read index beacon module 150 are both connected to the phase tracking module 160, the phase tracking module 160 is further connected to the write index logic module 120, the write index beacon module 140 is further in communication with the write index logic module 120, and the read index beacon module 150 is further in communication with the read index logic module 130.

The write index beacon module 140 is configured to generate a write beacon signal and cause the write beacon signal to toggle every time the write index logic module 120 writes the first pointer to the memory space corresponding to the target buffer address N times.

The read index beacon module 150 is configured to generate a read beacon signal, and cause the read beacon signal to be inverted each time the read index logic module 130 reads the first pointer from the memory space corresponding to the target cache address N times.

The target cache address corresponding to the write index logic 120 is the same as the target cache address corresponding to the read index logic 130, and may be any value of 0, 1, 2, 3, 4, or 5, and is not set to 1. N may be any positive integer, and is not 2.

Referring to fig. 3, when the write index logic module 120 writes a first pointer into the storage space corresponding to the target cache address 1, a write index signal Wbeacon generated by the write index beacon module 140 is turned over for the first time; counting is performed after the inversion, and when the write index logic module 120 writes the first pointer into the storage space corresponding to the target buffer address 12 times, the write pointer signal Wbeacon is inverted for the second time.

Referring to fig. 4, when the read index logic module 130 writes a first pointer into the storage space corresponding to the target cache address 1, a read beacon signal Rbeacon generated by the read index beacon module 150 is turned over for the first time; counting is performed after the inversion, and when the read index logic module 130 writes the first pointer into the storage space corresponding to the target cache address 1 for 2 times, the read beacon signal Rbeacon is inverted for the second time.

The read beacon signal Rbeacon generated by the read index beacon module 150 and the write beacon signal Wbeacon generated by the write index beacon module 140 can both be sent to the phase tracking module 160. Referring to fig. 2, M first registers 170 may be connected in series between the read index beacon module 150 and the phase tracking module 160. Each of the M first registers 170 includes an input terminal D, an output terminal Q, and a CLK terminal, and the CLK terminal of each first register 170 is connected to the fast clock cycle. The first register 170 may output the received data from its output terminal when it receives a rising edge signal at its CLK terminal.

Therefore, the M first registers 170 may delay the read beacon signal Rbeacon generated by the read index beacon module 150 by M fast clock cycles, and then transmit the delayed read beacon signal to the phase tracking module 160, so as to synchronize the read beacon signal from the slow clock domain to the fast clock domain.

If M is not set to 3, the read beacon signal Rbeacon is delayed by 3 fast clock cycles to obtain a delayed read beacon signal Rbeacon _ Sync, the phase tracking module 160 receives Rbeacon _ Sync, and the phase tracking module 160 delays the write beacon signal by the sum of M fast clock cycles and the first target delay time to obtain a delayed write beacon signal Wbeacon _ cmp in order to compare the write beacon signal Wbeacon with Rbeacon _ Sync. The first target delay time is not set to 2 fast clock cycles, and since M is 3, the phase tracking module 160 delays the write beacon signal Wbeacon by 5 fast clock cycles to obtain Wbeacon _ cmp.

The phase tracking module 160 may compare the delayed read beacon signal Rbeacon _ Sync and the delayed write beacon signal Wbeacon _ cmp and generate a corresponding write index control signal according to the comparison result.

Optionally, the generating of the corresponding write index control signal according to the comparison result may be specifically implemented by:

referring to fig. 5, if the transition point of the waveform of the delayed write beacon signal Wbeacon _ cmp is earlier than the transition point of the waveform of the read beacon signal Rbeacon _ Sync after delaying M fast clock cycles, a WrEarly signal is generated, where the WrEarly signal is a flag signal indicating that the time of writing the first pointer is earlier than the expected time, and the expected time is the time that satisfies the first target delay time.

Referring to fig. 6, if the transition point of the waveform of the delayed write beacon signal Wbeacon _ cmp is later than the transition point of the waveform of the read beacon signal Rbeacon _ Sync after delaying M fast clock cycles, a WrLate signal is generated, where the WrEarly signal is a flag signal indicating that the time of writing the first pointer is later than the desired time.

The phase tracking module 160 sends the generated WrEarly signal or WrLate signal to the write index logic module 120, and the write index logic module 120 adjusts the write timing according to the write index control signal.

Optionally, the write index logic module 120 adjusts the write time according to the write index control signal, and specifically includes the following steps: and when the count value is greater than or equal to 0, if the WrEearly signal is received, not reducing the value corresponding to the fast clock period when the count value is supposed to be reduced by the value corresponding to the fast clock period.

And when the count value is greater than or equal to 0, if a Wrlate signal is received, reducing the values corresponding to the two fast clock cycles when the count value is supposed to be reduced by the value corresponding to the fast clock cycle.

And when the count value is less than 0, adding the count value to a numerical value corresponding to the slow clock period so as to recover the state that the count value is greater than or equal to 0.

Referring to fig. 7, fig. 7 shows 6 AND gates, AND the count values of AND1, AND 2, AND3 in the 6 AND gates are greater than or equal to 0; AND 4, AND 5, AND 6 correspond to count values less than 0.

For AND1, under the condition: AND when the count value is greater than or equal to 0 AND the WrEearly signal is received, AND the count value is directly input into the AND1 again without executing the action when the count value is reduced by the value corresponding to the fast clock period.

For AND 2, under the condition: when the count value is greater than or equal to 0 and the WrLate signal is received, and the count value should be decreased by the value corresponding to the fast clock period, the subtracter 123 is used to decrease the values corresponding to the two fast clock periods based on the count value.

For AND3, under the condition: when the count value is greater than or equal to 0 and neither the WrEarly signal nor the WrLate signal is received, the count value is decreased by the subtractor 124 for a fast clock period when the count value should be decreased by the fast clock period.

For AND 4, under the condition: when the count value is smaller than 0 AND the received WrEarly signal is satisfied, the adder 127 is used to increase the current count value by a value corresponding to a slow clock cycle, AND then when the count value should be decreased by the value corresponding to the fast clock cycle, no action is performed, AND the count value is directly input into the AND 4 again.

For AND 5, under the condition: the count value is less than 0, and when the WrLate signal is received, the adder 127 is used to increase the current count value by a value corresponding to a slow clock period, and then when the count value should be decreased by a value corresponding to a fast clock period, the subtracter 125 is used to decrease the values corresponding to two fast clock periods based on the count value.

For AND 6, under the condition: when the count value is less than 0 and the WrEarly signal is not received and the WrLate signal is not received, the adder 127 is used to increase the current count value by a value corresponding to a slow clock cycle, and then when the count value should be decreased by the value corresponding to the fast clock cycle, the subtractor 126 is used to decrease the value corresponding to a fast clock cycle.

The result of any one of the six and gates is transmitted to the first DFF 121 through the OR gate OR, and is output by the first DFF 121 when a rising edge occurs in a fast clock cycle, and the output will return to the input terminals of the six and gates, and also when the count value is less than 0, the buffer address +1 pointed to by the write index logic module 120 to the storage space of the memory 110 will be selected through the selector MUX, and the buffer address pointed to by the write index logic module 120 will be stored through the second DFF 122.

The pointer synchronization apparatus 100 shown in fig. 2 further includes a fast handshake state machine 180 and a slow handshake state machine 190.

In the embodiment of the present application, the software needs to correctly configure the fast clock cycle and the slow clock cycle, and after the software configuration is completed, the write index logic module 120 and the read index logic module 130 may start to work. Since the registers of the fast clock cycle and the slow clock cycle are both in the fast clock domain, after the software configuration is completed, the fast handshake state machine 180 and the slow handshake state machine 190 of the fast clock domain handshake, and then the write index logic 120 and the read index logic 130 are started. In addition, if the write index logic module 120 and the read index logic module 130 are to be stopped, a Stop register (not shown) may be configured by software, and specifically, the Stop of the write index logic module 120 and the read index logic module 130 may be realized by handshaking of the fast handshake state machine 180 and the slow handshake state machine 190.

Referring to fig. 10, fig. 10 illustrates the handshaking process of the fast handshake state machine 180 and the slow handshake state machine 190 in one embodiment. The left side of fig. 10 is the state of the fast handshake state machine 180, the right side is the state of the slow handshake state machine 190, and the middle is the handshake signals between the two state machines. At time T1, the fast handshake state machine is reset and the fast handshake state machine is in an idle state. Outputs FastStopOut ═ 1 signal to the slow handshake state machine.

At time T2, the slow handshake state machine is reset and the slow handshake state machine is in an idle state. And outputting a SlowStopOut-1 signal to a fast handshake state machine.

At time T3, SlowStopOut reaches the fast handshake state machine. The fast handshake state machine confirms that the slow handshake state machine is in an idle state.

At time T4, FastStopOut reaches the slow handshake state machine. The slow handshake state machine confirms that the fast handshake state machine is in an idle state.

At time T5, the software configures the Stop register to 0 and the fast handshake state machine enters the wait clock cycle configuration state. The output FastStopOut is 0 and FastActOut is 1.

At time T6, FastStopOut ═ 0 reaches the slow handshake state machine. The slow handshake state machine confirms that the fast handshake state machine has entered the wait for clock cycle configuration state. The slow handshake state machine enters a wait for clock cycle configuration state. And the output SlowStopOut is 0.

At time T7, SlowStopOut reaches the fast handshake state machine, which confirms that the slow handshake state machine has entered the wait clock configuration state.

At time T8, the software has configured the clock cycle and has configured Freq _ Valid as 1. The fast handshake state machine enters the start write index logic state. Write index logic module 120 begins operation. Outputting FastAckOut to the slow handshake state machine as 0.

At time T9, the slow handshake state machine receives FastActOut which is 0, and confirms that the fast handshake state machine has entered the start-to-write index logic state and the start-to-read index logic state. The read index logic module 130 begins operation.

Referring to fig. 8, in an embodiment, the pointer synchronization apparatus 100 provided in the embodiment of the present application further includes: the register comprises a first conversion module 101, a second conversion module 103 and L second registers 102, wherein the L second registers 102 are sequentially connected between the first conversion module 101 and the second conversion module 103.

The first conversion module 101 is used for converting the second pointer running in the slow clock domain from binary code to gray code.

The L second registers 102 are configured to delay the gray code representing the second pointer by L fast clock cycles and then send the delayed gray code to the second conversion module 103.

The second conversion module 103 is configured to convert the gray code delayed by L fast clock cycles into a binary code, and output the binary code converted from the gray code to complete synchronization of the second pointer, where the L fast clock cycles are delay times of synchronization of the second pointer.

Alternatively, the clock domain crossing synchronization of the second pointer may be performed in the above manner, or may be performed in the following manner:

referring to fig. 11, in one embodiment, the pointer synchronization apparatus 100 may include a buffer 104, a slow-write index logic module 105, a fast-read index logic module 106, a slow-write index beacon module 107, a fast-read index beacon module 108, and a read phase tracking module 109. The slow-write index logic module 105 and the fast-read index logic module 106 are both connected to the buffer 104, the clock cycle of the slow-write index logic module 105 is the same as the slow clock cycle of the slow clock domain, and the clock cycle of the fast-read index logic module 108 is the same as the fast clock cycle of the fast clock domain.

The slow write index logic 105 is configured to write a second pointer into the buffer 104 according to the slow clock cycle.

The fast read index logic 106 is configured to determine a read time according to the fast clock cycle and the slow clock cycle, and read the second pointer from the buffer 104 at the read time.

The method by which the fast read index logic 106 determines the read time is similar to the method by which the write index logic 120 determines the write time. Every time a fast clock period passes, the accumulated value is reduced by a value corresponding to the fast clock period;

and judging whether the accumulated value is less than 0.

If the accumulated value is not less than 0, jumping to the step: every time a fast clock period passes, the accumulated value is reduced by a value corresponding to the fast clock period;

if the accumulated value is less than 0, reading a second pointer from the buffer 104, increasing the accumulated value by a value corresponding to the slow clock cycle, and then jumping to the step: every time a fast clock cycle passes, the accumulated value is decreased by the value corresponding to the fast clock cycle.

The slow write index beacon module 107 generates a slow write beacon signal. Similar to the write index block 140, the slow write pointer signal is toggled each time the slow write index logic 105 writes the second pointer to the memory space corresponding to the target buffer address N times. The waveform for generating the write beacon is shown in fig. 12.

The fast reading index beacon module 108 is configured to generate a fast reading beacon signal. And when the fast reading index logic module 106 reads the second pointer from the storage space corresponding to the target cache address for N times, the fast reading beacon signal is turned over. The waveform for generating the read beacon is shown in fig. 13.

The fast read beacon signal FRbeacon generated by the fast read index beacon module 108 and the slow write beacon signal SWbeacon generated by the slow write index beacon module 107 can both be sent to the read phase tracking module 109.

The slow write beacon signal SWBeacon generated by the slow write index beacon module 107 passes through the M DFFs 102 and is then transmitted to the read phase tracking module 109 to synchronize the slow write beacon signal from the slow clock domain to the fast clock domain.

If M is not set to 3, the delayed slow write flag signal is delayed by 3 fast clock cycles, and the delayed slow write flag signal is obtained, and the read phase tracking module 109 receives the delayed slow write flag signal, which is received as the switch _ Sync. The second target delay time is not set to be 2 fast clock cycles, the switch _ sync has been delayed by 3 fast clock cycles, and FRbeacon needs to be delayed by one fast clock cycle to obtain FRbeacon _ cmp. SWbeacon _ sync and FRbeacon _ cmp are compared in read phase tracking module 109. And generating a corresponding read index control signal according to the comparison result.

referring to fig. 14, if the turning point of the waveform of the delayed fast read beacon signal FRbeacon _ cmp is later than the turning point of the waveform of the delayed slow write beacon signal SWbeacon _ Sync after delaying M fast clock cycles, an RdLate signal is generated, where the RdLate signal is a flag signal indicating that the time point of reading the second pointer is later than the expected time, and the expected time is the time that satisfies the second target delay time.

Referring to fig. 15, if the turning point of the waveform of the delayed fast read beacon signal FRbeacon _ cmp is earlier than the turning point of the waveform of the delayed slow write beacon signal SWbeacon _ Sync after M fast clock cycles, an RdEarly signal is generated, where the RdEarly signal is a flag signal indicating that the time for reading the second pointer is earlier than the desired time.

The read phase tracking module 109 sends the generated RdLate signal or RdEarly signal to the fast read index logic module 106, and the fast read index logic module 106 adjusts the read time according to the read index control signal.

Optionally, the fast-reading index logic module 106 adjusts the reading time according to the read index control signal, and specifically includes the following steps: and when the accumulated value is greater than or equal to 0, if the RdEearly signal is received, if the accumulated value is supposed to be reduced by the value corresponding to the fast clock period, not reducing the value corresponding to the fast clock period.

And when the accumulated value is greater than or equal to 0, if an Rdlate signal is received, reducing the values corresponding to the two fast clock cycles when the accumulated value is supposed to be reduced by the value corresponding to the fast clock cycle.

And when the accumulated value is less than 0, adding the accumulated value to a value corresponding to the slow clock period to restore the state that the accumulated value is greater than or equal to 0.

Referring to fig. 16, 6 AND gates are shown, AND the cumulative values corresponding to AND 7, AND 8, AND9 of the 6 AND gates are greater than or equal to 0; the AND10, AND 11, AND12 correspond to the accumulated value being less than 0.

For AND 7, under the condition: when the accumulated value is greater than or equal to 0 AND the RdEearly signal is received, if the accumulated value is decreased by the value corresponding to the fast clock period, no action is executed, AND the accumulated value is directly input into the AND1 again.

For AND 8, under the condition: and when the accumulated value is greater than or equal to 0 and the received Rdlate signal is satisfied, reducing the values corresponding to the two fast clock periods on the basis of the accumulated value through a subtracter when the accumulated value is supposed to reduce the values corresponding to the fast clock periods.

For AND9, under the condition: and when the accumulated value is greater than or equal to 0 and the RdEearly signal is not received and the Rdlate signal is not received, reducing the value corresponding to one fast clock period by the subtracter when the accumulated value is supposed to reduce the value corresponding to the fast clock period.

For AND10, under the condition: when the accumulated value is less than 0 AND the RdEarly signal is received, the adder is used to increase the current accumulated value by a value corresponding to a slow clock period, AND then when the accumulated value is decreased by the value corresponding to the fast clock period, no action is executed, AND the accumulated value is directly input into the AND 4 again.

For AND 11, under the condition: when the accumulated value is less than 0 and the received Rdlate signal is satisfied, the adder is used to increase the current accumulated value by a value corresponding to a slow clock period, and then when the accumulated value is decreased by the value corresponding to the fast clock period, the subtracter is used to decrease the values corresponding to the two fast clock periods on the basis of the accumulated value.

For AND12, under the condition: when the accumulated value is less than 0 and the RdEarly signal is not received and the Rdlate signal is not received, the adder is used to increase the current accumulated value by a value corresponding to a slow clock period, and then when the accumulated value is decreased by the value corresponding to the fast clock period, the subtracter is used to decrease the value corresponding to a fast clock period.

The result of any one of the six and gates is transmitted to the third DFF123 through the OR gate OR, and is output by the third DFF123 when a rising edge occurs in a fast clock cycle, and the output will return to the input end of the six and gates, and will also select the cache address +1 pointed to by the fast-read index logic module 106 in the storage space of the cache 104 through the selector MUX when the accumulated value is smaller than 0, and store the cache address pointed to by the fast-read index logic module 106 through the fourth DFF 124.

Referring to fig. 9, fig. 9 shows an asynchronous FIFO circuit 10 according to an embodiment of the present application, where the asynchronous FIFO circuit 10 includes the pointer synchronization apparatus 100, the write pointer logic module 200, the write full flag logic module 300, the read pointer logic module 400, the read empty flag logic module 500, and the dual port memory 600.

The write pointer logic module 200 is configured to send the write pointer to the pointer synchronization apparatus 100, so that the pointer synchronization apparatus 100 obtains the synchronized write pointer, and send the synchronized write pointer to the read empty flag logic module 500.

The read empty flag logic module 500 is configured to determine whether the data in the dual-port memory 600 is read empty according to the synchronized write pointer and read pointer.

Optionally, the empty flag reading logic module 500 may receive the synchronized write pointer, and determine whether the address pointed by the synchronized write pointer is consistent with the address pointed by the read pointer, if so, it indicates that the dual port memory 600 is empty, and the empty flag reading logic module 500 may output an empty flag.

The read pointer logic module 400 is configured to send the read pointer to the pointer synchronization apparatus 100, so that the pointer synchronization apparatus 100 obtains the synchronized read pointer, and send the synchronized read pointer to the full flag logic module 300.

The full flag logic 300 is configured to determine whether the dual-port memory 600 is full of data according to the synchronized read pointer and write pointer.

Optionally, the full flag logic 300 may receive the synchronized read pointer, and determine whether the address pointed by the synchronized read pointer is consistent with the address pointed by the write pointer, if so, it indicates that the dual-port memory 600 is full, and the full flag logic 300 may output a full flag.

The dual-port memory 600 is configured to receive the write pointer of the write pointer logic module 200 and write data to a location pointed by the write pointer; and is further configured to receive the read pointer of the read pointer logic module 400 and read data from the location pointed to by the read pointer.

The synchronization from the write pointer to the clock domain where the read pointer is located and the synchronization from the read pointer to the clock domain where the write pointer is located can be performed by the pointer synchronization apparatus 100, and after the clock domain crossing synchronization is completed, the full flag logic module 300 performs the determination on whether the clock domain is full, and the empty flag logic module 500 performs the determination on whether the clock domain is empty. The existence of the pointer synchronization device 100 shortens the time difference from writing to reading of the same pointer, thereby accelerating the judgment of full writing or empty reading and improving the working efficiency of hardware.

The embodiment of the present application further provides a processor system (not shown), which includes an asynchronous FIFO circuit, a first electrical element (not shown), and a second electrical element (not shown), where the first electrical element and the second electrical element are communicated through the asynchronous FIFO circuit, the first electrical element operates in a fast clock cycle, and the second electrical element operates in a slow clock cycle.

Referring to fig. 17, fig. 17 is a flowchart illustrating a pointer synchronization method according to an embodiment of the present application, where the method is executed by the pointer synchronization apparatus 100, and specifically includes the following steps S110 to S120:

in step S110, the write index logic module 120 determines a write time according to the fast clock cycle and the slow clock cycle, and writes a first pointer into the memory 110 at the write time.

The memory 110 includes a predetermined number of memory spaces, each for storing a pointer; when writing the first pointer to the memory 110, the first pointer is sequentially written to one of the preset number of memory spaces in the memory 110 according to the writing time.

Alternatively, in a specific embodiment, please refer to fig. 18, fig. 18 shows specific steps of step S110, including the following steps S111 to S112.

And step S111, reducing the counting value by a value corresponding to the fast clock cycle every time one fast clock cycle passes, wherein the initial value of the counting value is a value corresponding to the slow clock cycle.

Step S112, when the count value is smaller than 0, writing a first pointer into the memory 110, and increasing the count value by a value corresponding to the slow clock cycle, where the time corresponding to the count value smaller than 0 is the writing time.

By the above method, the write index logic module 120 and the read index logic module 130 can work in respective clock cycles at similar speeds for writing the pointer data and reading the pointer data, which is more convenient for calculating the delay time.

Step S120, the index reading logic module 130 reads the first pointer from the memory 110 according to the slow clock cycle, and the writing time satisfies: such that the time difference between the same first pointer being written to memory 110 by the write index logic 120 and read from memory 110 by the read index logic 130 is a first target latency.

The clock cycle of the write index logic module 120 is the same as the fast clock cycle of the fast clock domain, the clock cycle of the read index logic module 130 is the same as the slow clock cycle of the slow clock domain, the write index logic module 130 determines the write time of writing the first pointer into the memory 110 according to the fast clock cycle and the slow clock cycle, the write index logic module 120 reads the first pointer from the memory 110 according to the slow clock cycle, the determination of the write time can make the time difference from writing to reading of the same first pointer be a first target delay time, the first target delay time is a delay time set by a user and is shorter than the delay time of synchronization of pointers across clock domains in the prior art, and therefore the requirement of a high-performance processor on low delay of data transmission can be met.

When the first pointer is read from the memory 110, the first pointer may be sequentially read from a preset number of storage spaces in the memory 110.

Referring to fig. 19, the embodiment of the present application further includes the following steps S210 to S230:

in step S210, the write index beacon module 140 generates a write beacon signal, and makes the write beacon signal flip every time the write index logic module 120 writes the first pointer into the storage space corresponding to the target buffer address N times.

In step S220, the index reading beacon module 150 generates a reading beacon signal, and when the index reading logic module 130 reads the first pointer from the memory space corresponding to the target cache address N times, the reading beacon signal is inverted.

In step S230, the phase tracking module 160 generates a write index control signal according to the write beacon signal and the read beacon signal, and sends the write index control signal to the write index logic module 120, so that the write index logic module 120 adjusts the write time.

The write index beacon module 140 may perform the inversion of the write beacon signal once when the write index logic module 120 writes the first pointer to the target buffer address N times, so as to generate the write beacon signal at the target buffer address by the inversion point; the read index beacon module 150 may perform one inversion of the read beacon signal every time the read index logic module 130 reads the first pointer from the storage space corresponding to the same target cache address N times, so as to generate the read beacon signal with the inverted point at the same target cache address. Both the write beacon signal and the read beacon signal may be passed to the phase tracking module 160 so that the phase tracking module 160 may generate a write index control signal according to the time difference between the two, and the write index control signal may be sent to the write index logic module 120 so that the write index logic module 120 may adjust the write time. The write time is adjusted by the feedback of the read beacon signal and the write beacon signal, so that the time difference from the writing to the reading of the same first pointer is stably maintained at the first target delay time, and the stability of the first target delay time is improved.

Optionally, before step S230, the following steps may be further included: the M first registers 170 delay the read beacon signal generated by the read index beacon module 150 by M fast clock cycles and then transmit the delayed read beacon signal to the phase tracking module 160, so as to synchronize the read beacon signal from a slow clock domain to a fast clock domain.

The read beacon signal may be synchronized by the M first registers 170 in order to compare the read beacon signal with the write beacon signal, and the read beacon signal is synchronized from the slow clock domain to the fast clock domain after delaying by M fast clock cycles.

Optionally, referring to fig. 20, the step S230 may specifically include the following steps S231 to S234:

step S231, delaying the write target signal by the sum of M fast clock cycles and the first target delay time to obtain a delayed write target signal.

Step S232, comparing the delayed write beacon signal with the read beacon signal delayed by M fast clock cycles.

Step S233, if the turning point of the waveform of the delayed write beacon signal is earlier than the turning point of the waveform of the read beacon signal delayed by M fast clock cycles, a WrEarly signal is generated, where the WrEarly signal is a flag signal indicating that the time of writing the first pointer is earlier than the expected time.

Step S234, if the turning point of the waveform of the delayed write beacon signal is later than the turning point of the waveform of the read beacon signal delayed by M fast clock cycles, generating a WrLate signal, where the WrEarly signal is a flag signal indicating that the time of writing the first pointer is later than the expected time.

After receiving the read beacon signal delayed by M fast clock cycles, the phase tracking module 160 delays the write beacon signal by M fast clock cycles, delays the write beacon signal by the first target delay time, compares the write beacon signal with the read beacon signal, and if the waveforms of the write beacon signal and the read beacon signal are aligned, it indicates that the time difference from writing to reading of the same first pointer is exactly the first target delay time; if the turning point of the waveform of the delayed write beacon signal is earlier than that of the waveform of the delayed read beacon signal, the writing time is earlier, and a corresponding write index control signal WrEearly signal is generated; if the inversion point of the delayed write beacon signal is later than the inversion point of the delayed read beacon signal, it indicates that the write time is later, and a corresponding write index control signal WrLate is generated.

The write index logic module 120 adjusts the write time according to the received write index control signal, which may specifically include the following steps: when the count value is greater than or equal to 0, if the write index logic module 120 receives a WrEarly signal, the operation of decreasing the value corresponding to the fast clock cycle is not performed when the count value should be decreased by the value corresponding to the fast clock cycle; when the count value is greater than or equal to 0, if the write index logic module 120 receives a WrLate signal, the count value is decreased by the value corresponding to the two fast clock cycles when the count value should be decreased by the value corresponding to the fast clock cycle; when the count value is smaller than 0, the write index logic module 120 adds the count value to a value corresponding to the slow clock cycle to recover the state where the count value is greater than or equal to 0.

When the count value is greater than or equal to 0 and the WrEarly signal is received, the write index logic module 120 does not perform an action of decreasing the value corresponding to the fast clock cycle when the count value should decrease the value corresponding to the fast clock cycle, so as to prolong the time when the count value reaches the state less than 0, and further postpone the writing time of writing the first pointer into the memory 110; when the count value is greater than or equal to 0 and the WrLate signal is received, and the count value is to be decreased by the value corresponding to the fast clock cycle, the write index logic module 120 additionally decreases the value corresponding to one fast clock cycle, so that the time for the count value to reach the state less than 0 is shortened, and the write time for writing the first pointer into the memory 110 is advanced; and when the count value is less than 0, adding the count value to a value corresponding to the slow clock period so as to restore the count value to be greater than or equal to 0. The write index logic module 120 adjusts the write time according to different write index control signals, so as to keep the time difference from being written to being read of the same first pointer stable and maintain the first target delay time.

In a specific implementation manner, the embodiment of the present application further includes the following steps: the first conversion module 101 converts the second pointer running in the slow clock domain from binary code to gray code; the L second registers 102 delay the gray code representing the second pointer by L fast clock cycles and then send the gray code representing the second pointer to the second conversion module 103; the second conversion module 103 converts the gray code delayed by L fast clock cycles into a binary code, and outputs the binary code converted by the gray code to complete the synchronization of the second pointer, wherein the L fast clock cycles are delay times of the synchronization of the second pointer.

For the second pointer synchronized from the slow clock domain to the fast clock domain, since the target clock domain is the fast clock domain, the synchronization between the two can be realized through the L second registers 102, and the synchronization across the clock domains of the second pointer still has a lower delay time under the condition of keeping the realization structure simple.

In a specific implementation manner, the pointer synchronization method provided in the embodiment of the present application may further include the following steps:

the slow writing index logic module writes a second pointer into the buffer according to the slow clock period; the fast reading index logic module determines reading time according to the fast clock period and the slow clock period, and reads a second pointer from the buffer at the reading time; wherein the readout timing satisfies: and the time difference from the time when the same second pointer is written into the buffer by the slow-writing index logic module to the time when the same second pointer is read out of the buffer by the fast-reading index logic module is a second target delay time.

The determination of the reading time may make the time difference from the time when the second pointer is written to the time when the second pointer is read be the second target delay time, which is the delay time set by the user, and may be shorter than the delay time of the pointer synchronization across clock domains in the prior art, for example, two fast clock cycles, so that the requirement of the high performance processor for low delay of data transmission may be satisfied.

In the embodiments provided in the present application, it should be understood that the disclosed apparatus and method may be implemented in other ways. The above-described embodiments of the apparatus are merely illustrative, and for example, the division of the units is only one logical division, and there may be other divisions when actually implemented, and for example, a plurality of units or components may be combined or integrated into another system, or some features may be omitted, or not executed. In addition, the shown or discussed mutual coupling or direct coupling or communication connection may be an indirect coupling or communication connection of devices or units through some communication interfaces, and may be in an electrical, mechanical or other form.

In addition, units described as separate parts may or may not be physically separate, and parts displayed as units may or may not be physical units, may be located in one place, or may be distributed on a plurality of network units. Some or all of the units can be selected according to actual needs to achieve the purpose of the solution of the embodiment.

Furthermore, the functional modules in the embodiments of the present application may be integrated together to form an independent part, or each module may exist separately, or two or more modules may be integrated to form an independent part.

In this document, relational terms such as first and second, and the like may be used solely to distinguish one entity or action from another entity or action without necessarily requiring or implying any actual such relationship or order between such entities or actions.

The above description is only an example of the present application and is not intended to limit the scope of the present application, and various modifications and changes may be made by those skilled in the art. Any modification, equivalent replacement, improvement and the like made within the spirit and principle of the present application shall be included in the protection scope of the present application.

Claims

1. A pointer synchronization device is characterized in that the device is used for realizing synchronization of pointers between different clock domains, the clock domains comprise a fast clock domain and a slow clock domain, the device comprises a memory, a write index logic module and a read index logic module, the memory is respectively connected with the write index logic module and the read index logic module, the clock cycle of the write index logic module is the same as the fast clock cycle of the fast clock domain, and the clock cycle of the read index logic module is the same as the slow clock cycle of the slow clock domain;

the write index logic module is used for determining write time according to the fast clock cycle and the slow clock cycle and writing a first pointer into the memory at the write time;

the read index logic module is used for reading a first pointer from the memory according to the slow clock period;

wherein the writing time satisfies: such that the time difference between the same first pointer being written to memory by the write index logic and being read from memory by the read index logic is a first target latency.

2. The pointer synchronization apparatus of claim 1, wherein the write index logic module is configured to: determining a write time according to the fast clock cycle and the slow clock cycle, and writing a first pointer into the memory at the write time, specifically including:

every time a fast clock period passes, reducing a counting value by a numerical value corresponding to the fast clock period, wherein the initial value of the counting value is a numerical value corresponding to the slow clock period;

and when the count value is smaller than 0, writing a first pointer into the memory, and increasing the count value by a numerical value corresponding to the slow clock period, wherein the time corresponding to the count value smaller than 0 is the writing time.

3. The pointer synchronization apparatus of claim 1, wherein the memory comprises a predetermined number of memory spaces, each of the memory spaces being used for storing a pointer;

the writing index logic module is specifically configured to sequentially write a first pointer into one of a preset number of storage spaces in the memory according to the writing time;

and the index reading logic module is used for sequentially reading a first pointer from one of the preset number of storage spaces in the memory according to the slow clock period.

4. The pointer synchronization apparatus of claim 3, wherein each of the memory spaces has a corresponding cache address, the apparatus further comprising: the system comprises a write index beacon module, a read index beacon module and a phase tracking module, wherein the write index beacon module and the read index beacon module are connected with the phase tracking module, and the phase tracking module is also connected with a write index logic module;

the write index beacon module is used for generating a write beacon signal and enabling the write beacon signal to be overturned when the write index logic module writes a first pointer into a storage space corresponding to a target cache address for N times;

the index reading beacon module is used for generating a beacon reading signal and enabling the beacon reading signal to be overturned when the index reading logic module reads the first pointer from the storage space corresponding to the target cache address for N times;

the phase tracking module is used for generating a write index control signal according to the write beacon signal and the read beacon signal and sending the write index control signal to the write index logic module so that the write index logic module adjusts the write time.

5. The pointer synchronization device of claim 4, further comprising M first registers, sequentially connected between the read index beacon module and the phase tracking module, for delaying the read beacon signal generated by the read index beacon module by M fast clock cycles before transmitting the delayed read beacon signal to the phase tracking module, so as to synchronize the read beacon signal from a slow clock domain to a fast clock domain.

6. The pointer synchronization apparatus as claimed in claim 5, wherein the phase tracking module is configured to generate a write index control signal according to the write beacon signal and the read beacon signal, and specifically comprises:

delaying the write mark signal by the sum of M fast clock periods and the first target delay time to obtain a delayed write mark signal;

comparing the delayed write beacon signal with the read beacon signal delayed by M fast clock periods;

if the turning point of the waveform of the delayed write beacon signal is earlier than the turning point of the waveform of the read beacon signal delayed by M fast clock periods, generating a WrEearly signal, wherein the WrEearly signal is a mark signal which represents that the time of writing the first pointer is earlier than the expected time;

and if the turning point of the waveform of the delayed write beacon signal is later than the turning point of the waveform of the read beacon signal delayed by M fast clock periods, generating a Wrlate signal, wherein the WrEearly signal is a mark signal which represents that the time of writing the first pointer is later than the expected time.

7. The pointer synchronization apparatus of claim 6, wherein the write index logic module is further configured to:

when the counting value is greater than or equal to 0, if a WrEearly signal is received, when the counting value is supposed to be reduced by the value corresponding to the fast clock period, the action of reducing the value corresponding to the fast clock period is not carried out;

when the counting value is greater than or equal to 0, if a Wrlate signal is received, reducing the values corresponding to the two fast clock cycles when the counting value is supposed to be reduced by the value corresponding to the fast clock cycle;

8. A pointer synchronization device is characterized in that the device is used for realizing synchronization of pointers among different clock domains, wherein each clock domain comprises a fast clock domain and a slow clock domain, the device comprises a buffer, a slow-write index logic module and a fast-read index logic module, the buffer is respectively connected with the slow-write index logic module and the fast-read index logic module, the clock cycle of the slow-write index logic module is the same as the slow clock cycle of the slow clock domain, and the clock cycle of the fast-read index logic module is the same as the fast clock cycle of the fast clock domain;

the slow writing index logic module is used for writing a second pointer into the buffer according to the slow clock period;

the fast reading index logic module is used for determining reading time according to the fast clock period and the slow clock period and reading a second pointer from the buffer at the reading time;

wherein the readout timing satisfies: and the time difference from the time when the same second pointer is written into the buffer by the slow-writing index logic module to the time when the same second pointer is read out of the buffer by the fast-reading index logic module is a second target delay time.

9. The pointer synchronization apparatus according to claim 8, wherein the fast-read index logic module is configured to determine a read time according to the fast clock cycle and the slow clock cycle, and read a second pointer from the buffer at the read time, and specifically includes:

every time a fast clock period passes, reducing the accumulated value by a numerical value corresponding to the fast clock period, wherein the initial value of the accumulated value is a numerical value corresponding to the slow clock period;

and when the accumulated value is smaller than 0, reading a second pointer from the buffer, and increasing the accumulated value by a value corresponding to the slow clock period, wherein the time corresponding to the accumulated value smaller than 0 is the reading time.

10. The pointer synchronization apparatus of claim 8, wherein the buffer comprises a predetermined number of buffer spaces, each buffer space being used for storing a pointer;

the slow-write index logic module is specifically configured to sequentially write a second pointer into one of a preset number of cache spaces in the cache according to the slow clock cycle;

and the index reading logic module is used for sequentially reading a second pointer from one of the preset number of cache spaces in the cache according to the reading time.

11. The pointer synchronization apparatus of claim 10, wherein each of the buffer spaces has a corresponding buffer address, the apparatus further comprising: the system comprises a slow-write index beacon module, a fast-read index beacon module and a read phase tracking module, wherein the slow-write index beacon module and the fast-read index beacon module are connected with the read phase tracking module, and the read phase tracking module is also connected with the fast-read index logic module;

the slow writing index beacon module is used for generating a slow writing beacon signal and enabling the slow writing beacon signal to be overturned when the slow writing index logic module writes a second pointer into a cache space corresponding to a target cache address for N times;

the fast reading index beacon module is used for generating a fast reading beacon signal and enabling the fast reading beacon signal to turn over when the fast reading index logic module reads a second pointer for N times from a cache space corresponding to the target cache address;

the read phase tracking module is used for generating a read index control signal according to the slow write beacon signal and the fast read beacon signal and sending the read index control signal to the fast read index logic module so that the fast read index logic module adjusts the read time.

12. The pointer synchronization apparatus as claimed in claim 11, further comprising M digital flip-flops, sequentially connected between the slow-write index beacon module and the read phase tracking module, for delaying the slow-write beacon signal generated by the slow-write index beacon module by M fast clock cycles before transmitting the delayed slow-write beacon signal to the read phase tracking module, so as to synchronize the slow-write beacon signal from the slow clock domain to the fast clock domain.

13. The pointer synchronization apparatus as claimed in claim 12, wherein the read phase tracking module is configured to generate a read index control signal according to the slow write beacon signal and the fast read beacon signal, and specifically comprises:

delaying the fast reading beacon signal by the difference between M fast clock cycles and the second target delay time to obtain a delayed fast reading beacon signal;

comparing the delayed fast reading beacon signal with the delayed slow writing beacon signal after M fast clock periods;

if the turning point of the waveform of the delayed fast reading beacon signal is earlier than the turning point of the waveform of the slow writing beacon signal after delaying M fast clock periods, an RdEearly signal is generated, and the RdEearly signal is a mark signal representing that the time for reading the second pointer is earlier than the expected time;

and if the turning point of the waveform of the delayed fast reading beacon signal is later than the turning point of the waveform of the slow writing beacon signal after delaying the M fast clock cycles, generating an Rdlate signal, wherein the Rdlate signal is a mark signal which represents that the time for reading the second pointer is later than the expected time.

14. The pointer synchronization apparatus of claim 13, wherein the fast-read index logic module is further configured to:

when the accumulated value is greater than or equal to 0, if an RdEearly signal is received, when the accumulated value is supposed to reduce the value corresponding to the fast clock period, the action of reducing the value corresponding to the fast clock period is not carried out;

when the accumulated value is greater than or equal to 0, if an Rdlate signal is received, reducing the values corresponding to the two fast clock cycles when the accumulated value is supposed to reduce the value corresponding to the fast clock cycle;

15. An asynchronous FIFO circuit comprising the pointer synchronization apparatus, the write pointer logic module, the write full flag logic module, the read pointer logic module, the read empty flag logic module, and the dual port memory of any one of claims 1-14;

the write pointer logic module is used for sending a write pointer to the pointer synchronization device so that the pointer synchronization device can obtain a synchronized write pointer and send the synchronized write pointer to the read empty mark logic module;

the read empty flag logic module is used for judging whether the data in the dual-port memory is read empty according to the synchronized write pointer and read pointer;

the read pointer logic module is used for sending the read pointer to the pointer synchronization device so that the pointer synchronization device can obtain a synchronized read pointer and send the synchronized read pointer to the write full flag logic module;

the write-full flag logic module is used for judging whether the dual-port memory is fully written with data according to the synchronized read pointer and write pointer;

the dual-port memory is used for receiving the write pointer of the write pointer logic module and writing data to the position pointed by the write pointer; and the read pointer logic module is also used for receiving the read pointer of the read pointer logic module and reading data from the position pointed by the read pointer.

16. A processor system comprising the asynchronous FIFO circuit of claim 15, a first electrical component, and a second electrical component, the first and second electrical components being in communication through the asynchronous FIFO circuit, the first electrical component operating in fast clock cycles and the second electrical component operating in slow clock cycles.

17. A pointer synchronization method is characterized in that a pointer synchronization device is used for realizing synchronization of pointers between different clock domains, wherein each clock domain comprises a fast clock domain and a slow clock domain, the pointer synchronization device comprises a memory, a write index logic module and a read index logic module, the memories are respectively connected with the write index logic module and the read index logic module, the clock cycle of the write index logic module is the same as the fast clock cycle of the fast clock domain, and the clock cycle of the read index logic module is the same as the slow clock cycle of the slow clock domain;

the method comprises the following steps:

the write index logic module determines write time according to the fast clock cycle and the slow clock cycle, and writes a first pointer into the memory at the write time;

the read index logic module reads a first pointer from the memory according to the slow clock period;

18. The method of claim 17, wherein the write index logic determines a write time based on the fast clock cycle and the slow clock cycle, and writes a first pointer to the memory at the write time, comprising:

19. The method of claim 17, wherein the memory comprises a predetermined number of memory spaces, each of the memory spaces for storing a pointer;

the writing a first pointer to the memory at the write time includes:

writing a first pointer into one of a preset number of storage spaces in the memory sequentially at the writing time;

the reading the first pointer from the memory according to the slow clock cycle includes:

and sequentially reading the first pointer from one of the preset number of storage spaces in the memory according to the slow clock period.

20. The method of claim 19, wherein each of the memory spaces has a corresponding cache address, and wherein the pointer synchronization apparatus further comprises: the system comprises a write index beacon module, a read index beacon module and a phase tracking module, wherein the write index beacon module and the read index beacon module are connected with the phase tracking module, and the phase tracking module is also connected with a write index logic module;

the method further comprises the following steps:

the write index beacon module generates a write beacon signal, and when the write index logic module writes a first pointer into a storage space corresponding to a target cache address for N times, the write beacon signal is enabled to be overturned;

the index reading beacon module generates a beacon reading signal, and when the index reading logic module reads a first pointer from a storage space corresponding to the target cache address for N times, the beacon reading signal is turned over;

and the phase tracking module generates a write index control signal according to the write beacon signal and the read beacon signal and sends the write index control signal to the write index logic module so that the write index logic module adjusts the write time.

21. The method of claim 20, wherein the pointer synchronization apparatus further comprises: the M first registers are sequentially connected between the read index beacon module and the phase tracking module, and before the phase tracking module generates a write index control signal according to the write beacon signal and the read beacon signal and sends the write index control signal to the write index logic module, the method further comprises:

and the M first registers delay the reading beacon signals generated by the reading index beacon module by M fast clock cycles and then transmit the reading beacon signals to the phase tracking module so as to realize the synchronization of the reading beacon signals from a slow clock domain to a fast clock domain.

22. The method of claim 21, wherein the phase tracking module generates a write index control signal based on the write beacon signal and the read beacon signal, comprising:

23. The method of claim 22, further comprising:

when the count value is greater than or equal to 0, if the write index logic module receives a WrEarly signal, the write index logic module does not perform an action of reducing the value corresponding to the fast clock cycle when the count value is supposed to reduce the value corresponding to the fast clock cycle;

when the count value is greater than or equal to 0, if the write index logic module receives a WrLate signal, reducing the values corresponding to the two fast clock cycles when the count value is to be reduced by the value corresponding to the fast clock cycle;

and when the count value is less than 0, the write index logic module adds the count value to a numerical value corresponding to the slow clock period so as to recover the state that the count value is greater than or equal to 0.

24. A pointer synchronization method is characterized in that a pointer synchronization device is used for realizing synchronization of pointers between different clock domains, wherein each clock domain comprises a fast clock domain and a slow clock domain, the device comprises a buffer, a slow-write index logic module and a fast-read index logic module, the buffers are respectively connected with the slow-write index logic module and the fast-read index logic module, the clock cycle of the slow-write index logic module is the same as the slow clock cycle of the slow clock domain, and the clock cycle of the fast-read index logic module is the same as the fast clock cycle of the fast clock domain;

the method comprises the following steps:

the slow writing index logic module writes a second pointer into the buffer according to the slow clock period;

the fast reading index logic module determines reading time according to the fast clock period and the slow clock period, and reads a second pointer from the buffer at the reading time;