CN203812025U

CN203812025U - Multi-serial-port parallel processing framework based on a SoC FPGA

Info

Publication number: CN203812025U
Application number: CN201320833956.0U
Authority: CN
Inventors: 刘玉升; 王楠
Original assignee: State Nuclear Power Automation System Engineering Co Ltd
Current assignee: State Nuclear Power Automation System Engineering Co Ltd
Priority date: 2013-12-18
Filing date: 2013-12-18
Publication date: 2014-09-03
Anticipated expiration: 2023-12-18

Abstract

The utility model belongs to the technical field of distributed industrial control and relates to a multi-serial-port parallel processing framework based on a SoC FPGA. The framework comprises transceivers and a SoC FPGA chip integrated with an FPGA and a processor CPU. The framework is characterized in that a plurality of UART cores and a plurality of coprocessor MCUs corresponding to the UART cores are designed in the FPGA in the SoC FPGA chips by means of a hardware description language; a plurality of embedded memories corresponding to the coprocessor MCUs are embedded into the FPGA and each embedded memory is configured to be in a dual-port mode capable of reading and writing; and the plurality of UART cores and a plurality of corresponding transceivers are connected through RS232/RS422/RS485 interfaces. The multi-serial-port parallel processing framework is high in system integration degree, low in hardware design cost, and capable of effectively reducing CPU load, promoting the transmission bandwidth of serial bus data, and flexibly expanding a plurality of serial channels.

Description

A kind of many serial ports parallel processing framework based on SoC FPGA

Technical field

The utility model belongs to distributing industrial control technology field, is specifically related to a kind of many serial ports parallel processing framework based on SoC FPGA.

Background technology

UART (universal asynchronous receiving-transmitting transmitter) is a kind of serial transmission interface that is widely used in short distance, low-speed communication, it is simple to operate, reliable operation, anti-interference strong, cost is low, long transmission distance (composition 485 networks can transmit more than 1,200 meter).In data communication, computer network and distributing industrial control system, processor often adopts serial communication and peripheral module swap data and information.

In modern industrial control system, multi-serial communication application is more and more extensive.Especially data collecting field, in engineering application, to the increase in demand of serial ports quantity, processor needs Real-time Collection and processes the data that come from multiple serial peripherals.Universal serial port implementation as shown in Figure 1.The serial ports limited amount that can provide due to ordinary processor or ASIC, in the time that the serial terminal of needs control exceedes more than four, traditional framework is just difficult to meet application request, as hardware cost costliness, be difficult to expansion, the problem such as power consumption is higher, data processing real-time is not high, processor load is high, UART bus bandwidth is low.Be in particular in: 1) serial peripheral is used RS232 or RS422/485 Asynchronous Serial Interface, generally adopting special integrated circuit is that UART chip is realized.As 8250, the chip such as 16550AFN is all common UART device, but this class device hardware serial line interface resource-constrained, and inner structure design is quite complicated, chip pin is more, what have contains many supplementary modules (as FIFO), in the time that reality is used, often only use UART basic function, when design, use this class chip, caused the wasting of resources; 2) what processor or special many serial port chip provided can extended serial port limited amount, cannot realize more UART serial ports expansion; 3) peripheral interface circuit complexity, board design difficulty is larger; 4) use UART chip also can make hardware cost increase and increase the area of circuit board, cannot large-scale application in multi-channel data acquisition occasion; 5) processor adopting serial mode scans each passage successively, but the too low CPU waits for too long that causes of serial communication speed is difficult to the higher actual demand that needs parallel processing of requirement of real time.

Summary of the invention

In view of the above-mentioned problems in the prior art, the technical problems to be solved in the utility model be to provide a kind of cost of hardware design low, can effectively reduce cpu load, can flexible expansion multi-path serial passage many serial ports parallel processing framework.

In order to realize above object, the technical solution adopted in the utility model is: a kind of many serial ports parallel processing framework based on SoC FPGA, the SoC fpga chip that comprises transceiver, integrated field programmable gate array FPGA and processor CPU, is characterized in that: multiple UART core and the multiple coprocessor MCUs corresponding with each UART nuclear phase are designed by hardware description language in the FPGA inside in described SoC fpga chip; The embedded multiple and in-line memory that each coprocessor MCU is corresponding of described FPGA, each in-line memory is configured to dual-port pattern that can read-write operation; Described multiple UART core connects by RS232/RS422/RS485 interface with multiple corresponding described transceivers.

The multi-path serial passage being connected to form successively by corresponding UART core, coprocessor MCU and in-line memory in described SoCFPGA chip, each passage is independent mutually, and the CPU in SoC fpga chip can be scanned simultaneously and process the peripheral hardware information of all passages by internal bus.

Described coprocessor MCU completes data link layer work, and the processor CPU in described SoC fpga chip completes application layer work.

Good effect of the present utility model is: 1) utilize fpga logic resource rich in SoC FPGA can easily realize multichannel UART controller, according to requirement of engineering, only need amendment fpga logic can build flexibly many coprocessors MCU and many UART core, increase and decrease serial-port quantity, has improved level of integrated system greatly flexibly; 2), up to 16 and even when 32 serial-port, board periphery circuit design complexity and difficulty reduce greatly, greatly reduce expensive hardware cost, can large-scale application in multi-channel data acquisition occasion; 3) between the processor CPU in SoC FPGA and UART controller, be provided with the coprocessor MCU of multiple independent parallels; coprocessor MCU completes data link layer work; processor CPU is mainly responsible for application layer work; this framework can allow the serial peripheral of all passages of processor parallel scan; greatly reduce the load of CPU, promote serial bus data transmission bandwidth; 4) coordinate outside transceiving chip according to requirement of engineering, SoC FPGA only need slightly make communications protocol and the baud rate that logic Modification can support that RS232/RS422/RS485 is different flexibly.

Brief description of the drawings

Below in conjunction with the drawings and specific embodiments, the utility model is described in further detail.

Fig. 1 is existing universal serial port implementation schematic diagram;

Fig. 2 is the configuration diagram that the utility model SoC FPGA controls eight channel parallel scan process simultaneously;

Fig. 3 is CPU and the MCU residing network model position view of working in SoC FPGA.

Embodiment

In order to realize the support of parallel multi-channel serial peripheral, increase UART bus serial communication bandwidth, reduce the load of CPU, improve level of integrated system, reduction hardware cost, as shown in Figure 2, the many serial ports parallel processing framework of the utility model based on SoCFPGA, comprise transceiver, the SoC fpga chip of integrated field programmable logic array (FPLA) FPGA and processor CPU, CPU is connected with FPGA by internal bus, it is characterized in that: multiple UART core and the multiple coprocessor MCUs corresponding with each UART nuclear phase are designed by hardware description language in the FPGA inside in described SoC fpga chip, the embedded multiple and in-line memory that each coprocessor MCU is corresponding of described FPGA, each in-line memory is configured to dual-port pattern that can read-write operation, described multiple UART core connects by RS232/RS422/RS485 interface with multiple corresponding described transceivers.

Described SoC fpga chip is inner integrated monokaryon or polycaryon processor and field programmable gate array FPGA, interconnected by internal bus between processor CPU and FPGA.

The multi-path serial passage being connected to form successively by corresponding UART core, coprocessor MCU and in-line memory in described SoCFPGA chip, each passage is independent mutually, and CPU can scan simultaneously and process the peripheral hardware information of all passages.

Described coprocessor MCU completes data link layer work, and the processor CPU in described SoC fpga chip completes application layer work (as shown in Figure 3).

In the utility model, SoCFPGA realizes many UART interface, many coprocessors processing mode, can build flexibly many coprocessors MCU and many UART core by SoCFPGA, the UART core that SoCFPGA builds is connected by RS232/RS422/RS485 with outside transceiver, like this can flexible expansion multi-path serial passage.

Processor CPU in SoC FPGA reads, sends data by internal bus from FPGA.CPU is mainly responsible for application layer work.

The embedded in-line memory of SoCFPGA chip, be configured to can read-write operation real dual-port pattern (as the Dual Port in Fig. 2), or the data accepted to be sent in order to buffer memory.

Coprocessor MCU is the virtual coprocessor building by SoCFPGA, mainly completes data link layer work, processes after the data that come from UART core are maybe processed the parallel data that comes from Dual Port and sends to UART core.

UART examines and has showed UART function, and efficient transmitting-receiving serial data under the control of coprocessor MCU is provided and the UART interface of outside serial ports transceiver.

Transceiver is UART interface chip, mainly completes the conversion between RS232/RS422/RS485 level and TTL/COMS level.SoC FPGA processor and terminal all adopt Transistor-Transistor Logic level and positive logic, and level and negative logic that they and EIA adopt are incompatible, need in interface circuit, change.

In order to improve the integrated level of system, support multidiameter delay independence serial ports, improve UART bus bandwidth, reduce the load of CPU, reduction hardware cost, the utility model uses the field programmable gate array FPGA in SoCFPGA to build multiple UART core, and according to engineering, application needs only to need change programmed logic can increase and decrease flexibly serial-port quantity.On-site programmable gate array FPGA in SoC FPGA is made up of configurable logic module, input/output module and interconnector.FPGA utilizes look-up table (LUT) to realize combinational logic, and then drives other logical circuit and I/O interface, and the programming data that is stored in inner static storage cell determines the annexation between logic function and each module of each logical block.In the multiple combinatorial logic unit that work alone of FPGA internal configurations, realize multi-channel parallel UART communication function by hardware description language.As shown in Fig. 2, multiple UART core and multiple coprocessor MCU are designed respectively by hardware description language in the FPGA inside in SoCFPGA, and in-line memory embedded FPGA be can be configured to multiple real dual-ported memories.The advantage such as the method has that integrated level is high, volume is little, low in energy consumption and speed is fast, but also can be reconstructed systemic-function according to user's demand.

In many serial port data acquisitions application, what needs were real-time carries out data acquisition, serial terminal is controlled in real time.In traditional multi-channel serial framework, CPU is the state of inquiring about successively each serial port, and the each port of sequential scanning cause CPU to expend a large amount of time and resource, and universal serial bus bandwidth reduces along with the increase of number of channels.The method adopting in the utility model is: the FPGA inside in SoCFPGA builds multiple coprocessor MCU by hardware description language, and in-line memory embedded FPGA is configured to multiple real dual-ported memories.Coprocessor mainly completes data link layer work (as Fig. 3), processes after the data that come from UART core are maybe processed the parallel data that comes from Dual Port and sends to UART core.While accepting data, after coming from the data processing of UART core, be buffered in Dual Port in parallel data mode, corresponding Dual Port can send receive interruption request to CPU, CPU can complete response interruption after current task, then once read the data that come from Dual Port, CPU waits for that without spending a lot of time the UART core of low speed is sent completely data again.CPU only need be responsible for application layer work, has reduced the load of CPU.

While sending data, the all passages of processor CPU parallel scan in SoC FPGA, inquire after the request transmission status information that comes from certain passage, by the data buffer storage of certain passage given to be sent in the Dual of respective channel Port storer, once the coprocessor of respective channel inquires the data that have processor to send in corresponding Dual Port, startup work is immediately carried out exporting to UART core after respective handling.Processor also can once send to data of giving serial peripheral to be sent in Dual Port on all passages, then supply the coprocessor processing on each passage, processor can go deposit data to process other task after in the Dual Port on each passage immediately, wait for that without spending a lot of time again the UART of low speed accepts, and greatly reduces load and the stand-by period of processor like this.Coprocessor MCU in the utility model and Dual Port can real-time high-efficiency the data by be sent export to UART core, or data to be received processor are left in real time in the Dual Port of respective channel, each serial-port is completely independent, is independent of each other.

Data transfer bandwidth is the bottleneck of serial communication, and serial-port quantity more multi-band is wide lower.The many serial ports parallel processing framework based on SoC FPGA the utility model proposes has been introduced coprocessor MCU and Dual Port storer, can allow CPU at a high speed efficiently send data to the UART core of low speed, or reception in real time comes from the data of UART peripheral hardware, each passage is all established data buffer storage storer Dual port, coprocessor MCU, each passage is independent mutually, concurrent working.On universal serial bus, data bandwidth is the summation of maximum bandwidth on all passages, and for 8 road RS422, bus bandwidth can be up to 64Mbit/s.

The flexible support of serial communication is also the desired function of serial communication.Except conventional RS232 standard, also have RS422, RS485 standard, special UART chip seldom has can support RS232/RS422/RS485 simultaneously, even if there is the special UART chip that can support three kinds of communications protocol simultaneously, its price is also more expensive, and dirigibility and cost performance are low.

In the utility model, realize multiple UART core working alone and soft core coprocessor MCU in SoCFPGA inside by hardware description language, the communication protocol of data link layer is operated in MCU and realizes, coordinate outside transceiving chip according to requirement of engineering, SoCFPGA only need slightly make logic Modification can support different communications protocol, baud rate.

Claims

1. the many serial ports parallel processing framework based on SoC FPGA, the SoC fpga chip that comprises transceiver, integrated field programmable gate array FPGA and processor CPU, is characterized in that: the FPGA inside in described SoC fpga chip comprises multiple UART core and the multiple coprocessor MCUs corresponding with each UART nuclear phase; The embedded multiple and in-line memory that each coprocessor MCU is corresponding of FPGA; Described multiple UART core connects by RS232/RS422/RS485 interface with multiple corresponding described transceivers.

2. require described a kind of many serial ports parallel processing framework based on SoC FPGA according to right 1, it is characterized in that: the multi-path serial passage being connected to form successively by corresponding UART core, coprocessor MCU and in-line memory in the FPGA in described SoC fpga chip, each passage is independent mutually.