CN105632548A

CN105632548A - EMB configuration chain structure and configuration method of configuration chain

Info

Publication number: CN105632548A
Application number: CN201410601612.6A
Authority: CN
Inventors: 李大伟; 刘明
Original assignee: Capital Microelectronics Beijing Technology Co Ltd
Current assignee: Capital Microelectronics Beijing Technology Co Ltd
Priority date: 2014-10-30
Filing date: 2014-10-30
Publication date: 2016-06-01
Anticipated expiration: 2034-10-30
Also published as: CN105632548B

Abstract

The present invention relates to an EMB configuration chain structure and a configuration method of a configuration chain. The configuration chain includes at least two EMBs that are cascaded. Each EMB includes a configuration controller and a static random access memory (SRAM). Input data of a configuration data input port of the EMB configuration chain is written in a corresponding SRAM according to control of the configuration controller of each EMB; and data stored in the SRAM of the current EMB is output to next cascaded EMB according to control of the configuration controller of the current EMB, or is output through the configuration data output port of the EMB configuration chain.

Description

A kind of in-line memory EMB configures chain structure and collocation method

Technical field

The present invention relates to IC design technical field, particularly a kind of in-line memory EMB configures chain structure and collocation method.

Background technology

For field programmable gate array (FieldProgrammableGateArray, FPGA) chip, the in-line memory (EMB) in fpga chip is a critically important module. In general, the core of EMB is the SRAM (SRAM) of dual-port, having a lot of selectores (MUX) outside SRAM and configure the mode of operation of SRAM, including bit wide, position is deep, clock (clock) selects, the functions such as selection are deposited in output.

Fpga chip powers on both of which afterwards: configuration mode and user model. Under normal circumstances, during configuration mode, it is necessary to each configurable module within fpga chip is configured as desired state, the configuration to EMB is wherein also included. Usual way is to be controlled by the configuration control module that the configuration port of EMB is connected within FPGA. The configuration of EMB includes two parts: the configuration of EMB mode of operation and the configuration to SRAM initial value. Wherein the configuration of EMB mode of operation is likely to adopt shift register chain to configure, it is also possible to use configuration memorizer to configure. But the configuration of SRAM initial value can not adopt configuration memorizer configure, this is because writing of SRAM the sequential of as request just must can complete the configuration of initial value, and use that to configure memorizer be to be done directly desired modularization design; Additionally the configured length of initial value is relevant with the size of SRAM itself, such as 18Kbit, and such substantial amounts of configuration data is not suitable for using configuration memorizer that it is configured.

The configuration data of FPGA can be stored in off-chip nonvolatile storage, and after powering on, the Configuration Control Unit within FPGA reads the data of off-chip nonvolatile storage, is distributed to different configuration interfaces according to the interface sequence of agreement after analysis.

But it is as the continuous expansion of fpga chip scale, the number of EMB module also constantly increases, if the configuration port of each EMB being all connected to configuration control module be controlled, the quantity of these lines, by being very huge, is highly detrimental to the integrated of fpga chip top layer.

Summary of the invention

The invention provides a kind of in-line memory EMB and configure chain structure and collocation method, EMB is integrated with the cascade structure configuring chain, can effectively reduce the interface line quantity between Configuration Control Unit and EMB, thereby reduce the line of chip top-layer, reduce the complexity of design.

Embodiments provide in-line memory EMB in a kind of fpga chip and configure chain structure, including: at least two EMB that cascade connects;

Each described EMB includes: Configuration Control Unit and SRAM SRAM;

The control of the described Configuration Control Unit according to described each EMB, the input data of the configuration data input port that described EMB configures chain write corresponding SRAM; And the data of storage in the described SRAM of current EMB are exported to the next EMB of cascade by the control according to the described Configuration Control Unit of current EMB, or configured the configuration data output port output of chain by described EMB.

Preferably, described Configuration Control Unit includes: configuration mode depositor;

When configuration mode selects enable signal cf_ms effective, each described configuration mode depositor receives the described EMB input data configuring the configuration data input port serial input of chain, and is stored as configuration mode selection signal respectively.

It is further preferred that described Configuration Control Unit also includes: bypass register, configuration data register, SRAM write data register, SRAM read data register and position data depositor;

When enabling signal cf-en and being effective, select any one registers in bypass register, configuration data register, SRAM write data register, SRAM read data register or position data depositor described in signal behavior according to the described configuration mode of current EMB.

It is further preferred that the position data of storage is for indicating described EMB to configure the positional information in chain at described EMB in described position data depositor.

It is further preferred that when selecting SRAM write data register work described in signal behavior according to described configuration mode, described SRAM write data register, from the input data of the following bit position of described position data, detects the bit wide of described input data;

When described bit wide reaches specified width, which width, the input data detected within the scope of described bit wide are write in SRAM;

Wherein, often performing write-once, in SRAM, the storage address of write data is incremented by 1.

It is further preferred that when selecting SRAM read data register work described in signal behavior according to described configuration mode, the data of certain bit wide are read in the detection of described SRAM read data register from a storage address of SRAM, and transfer Serial output to;

Wherein, often performing once to read, the storage address reading data from SRAM is incremented by 1.

Second aspect, embodiments provides a kind of in-line memory EMB as described in above-mentioned first aspect and configures the collocation method of chain, and described method includes:

Position data register is configured, it is determined that described EMB configures the cascade connection of each EMB in chain;

When configuration mode selects enable signal cf_ms effective, configuration mode depositor is configured;

Configuration mode according to the output of configuration mode depositor selects signal and enables signal cf-en, select configuration data register is configured, or by SRAM write data register, SRAM is configured, or select to read the data in configuration data register, or read the data in SRAM by SRAM read data register.

Preferably, when described EMB configures in chain, one EMB selects signal according to the configuration mode that the configuration mode depositor in current EMB exports and enables signal cf-en, select by SRAM write data register described in current EMB, described SRAM to be configured, or read in described SRAM by described SRAM read data register data time, described method also includes:

Being configured by described EMB in chain, the configuration mode in the configuration mode depositor of other EMB except described current EMB selects signal to be configured for selecting the configuration mode of bypass register work to select signal.

The in-line memory EMB that the embodiment of the present invention provides configures chain structure and collocation method, by EMB is integrated with the cascade structure configuring chain, can effectively reduce the interface line quantity between Configuration Control Unit and EMB, thereby reduce the line of chip top-layer, reduce the complexity of design.

Accompanying drawing explanation

The EMB that Fig. 1 provides for the embodiment of the present invention configures chain structure schematic diagram;

The internal structure schematic diagram of the EMB that Fig. 2 provides for the embodiment of the present invention;

The structural representation of the Configuration Control Unit that Fig. 3 provides for the embodiment of the present invention;

The logical schematic that the SRAM write that Fig. 4 provides for the embodiment of the present invention enters.

Detailed description of the invention

Below by drawings and Examples, technical scheme is described in further detail.

The EMB that the embodiment of the present invention provides configures chain and is made up of at least two EMB of cascade. In a kind of fpga chip that Fig. 1 provides for the embodiment of the present invention, EMB configures the schematic diagram of chain structure. In example as shown in Figure 1, EMB configures chain and includes the EMB of 16 cascades successively.

EMB configures clock signal cf_clk in chain, configuration mode selects to enable signal cf_ms, enable signal cf-en, reset signal cf_rstn is transmitted as shown in FIG. from right to left by buffer one-level one-level, the input data cf_in of configuration data input port is under the sampling of clock signal cf_clk, select enable signal cf_ms and enable the setting of signal cf-en according to configuration mode, carry out the configuration data write under corresponding EMB mode of operation or SRAM initial value configuration mode, or carry out the configuration data reading etc. under corresponding EMB mode of operation or SRAM initial value configuration mode.

Include some with the EMB of existing FPGA inside EMB in chain structure the difference is that, EMB of the present invention configures and control logics. For a better understanding of the present invention, the EMB first embodiment of the present invention provided configures the internal structure of each EMB in chain structure and is introduced.

As in figure 2 it is shown, the EMB of the embodiment of the present invention includes: Configuration Control Unit 1, SRAM2 and user control interface 3.

User control interface 3 is connected with outside user interface.

Configuration Control Unit 1 is connected with outside configuration interface, is used for receiving by configuring the control logic that interface inputs, for selecting the execution read-write logic of configuration data register, SRAM write in Configuration Control Unit 1 to control logic or SRAM reading control logic. These logics can especially by arranging a configuration mode depositor and the corresponding signal that enables realizes, after can be described in detail.

It is connected to the input of SRAM by the output of the alternative gate mux in figure, the signals such as clock, enable, data input are provided for SRAM. Wherein, mux the SRAM write of gating Configuration Control Unit 1 can control logic or user control interface 3 and be connected to the data-out pin of SRAM, and the data output pins of SRAM is connected to the SRAM of Configuration Control Unit 1 and reads to control logic and user control interface 3. EMB configures the input data of the configuration data input port that EMB according to the control of the Configuration Control Unit 1 of each EMB, can be configured chain by chain and writes corresponding SRAM2; And the data of storage in the SRAM2 of current EMB are exported to the next EMB of cascade by the control according to the Configuration Control Unit 1 of current EMB, or configured the configuration data output port output of chain by EMB.

The internal structure of Configuration Control Unit 1 can specifically as it is shown on figure 3, include configuration mode depositor 11, bypass register 12, configuration data register 13, SRAM write data register 14, SRAM read data register 15, position data depositor 16 and a MUX 17;

When configuration mode selects enable signal cf_ms effective, the configuration mode depositor 11 of one EMB is selected, MUX 17 is controlled to choose the output of configuration mode depositor 11 simultaneously, and it is cascaded to the input of the configuration mode depositor 11 of next EMB, make EMB configure the configuration mode depositor cascade in chain and form configuration mode chain of registers, being connected between cf_in and cf_out, desired value can be sent in the configuration mode depositor 11 of EMB by now outside configuration module. Then, when enabling signal cf-en and being effective, any one registers in signal behavior bypass register 12, configuration data register 13, SRAM write data register 14, SRAM read data register 15 or position data depositor 16 is selected according to the configuration mode of current EMB.

Before other depositors are configured, it is necessary first to position data register 16 is configured. This is because EMB configures the cascade connection in chain at EMB, it is by the configuration of position data register 16 is determined. The Configuration Values of storage in position data depositor 16, is this EMB and configures location in chain at EMB.

The method that the configuration of position data register 16 can be adopted serial date transfer, disposable configure the position data depositor 16 of all EMB in chain and configures EMB. Can be specifically when cf-en is effective, configuration mode depositor 11 is configured the configuration mode of output and selects signal control MUX 17 to select all to be connected between cf-in and cf-out position data depositor 16, is configured by serial date transfer. After position data register 16 has configured, it is possible to EMB mode of operation is configured or SRAM is configured with.

It should be noted that in order to ensure not have the retention time to run counter to, defining the cf_in within each EMB in the present embodiment is that the rising edge by cf_clk gathers, cf_out is transmitted toward current EMB is outside by the trailing edge of cf_clk. Certainly, the clock control mode of the present invention is not limited to above-mentioned this, only illustrates for example in the above described manner in the present embodiment.

Assume that, in a concrete implementation scheme, the definition that selection of configuration signal selects with the configuration mode of corresponding registers is as shown in table 1 below.

Selection of configuration signal	Configuration mode	Describe
			0000	Bypass	Select bypass register 12
0001	EMB mode of operation	Option and installment data register 13, reads or writes
			0010	Write SRAM initial value	SRAM write data register 14 is selected to carry out SRAM write operation
0011	Read SRAM initial value	SRAM read data register 15 is selected to carry out SRAM read operation
			0100	Allocation position data	Position data depositor 16 is selected to configure
others	Bypass	Select bypass register 12

Table 1

Based on above-mentioned table 1, can respectively as described in following several situations to the collocation method of each depositor.

The first situation, the configuration process to position data register, it is possible to for:

First, configuration mode is selected enables signal cf_ms and is set to effectively, under the triggering of the signal rising edge of cf-clk, write 0100 by mono-Bits Serial of cf-in in the configuration mode depositor 11 of each EMB. Namely the EMB in EMB configuration chain passes through the output of MUX 17 strobe position data register 16. It should be noted that can be big-endian write to write data in each depositor, it is also possible to be little-endian write, only need to provide. In the present invention, what we adopted is first send a high position, after send the method for writing data of low level. Then, configuration mode selects enable signal cf_ms be set to invalid, and enable signal cf-en is set to effectively. Under the triggering of the signal rising edge of cf-clk, by position data depositor 16 write data to each EMB of mono-Bits Serial of cf-in. Further, under the triggering of the trailing edge of cf-clk signal, by the output of one Bits Serial of data in the position data depositor 16 of EMB. From there through a rising edge and a trailing edge, it is possible to make data move one in position data register 16, until completing whole EMB to configure the configuration of position data depositor 16 in chain.

The second situation, the configuration process to EMB mode of operation, it is possible to for:

First, configuration mode is selected enables signal cf_ms and is set to effectively, under the triggering of the signal rising edge of cf-clk, write 0001 by mono-Bits Serial of cf-in in the configuration mode depositor 11 of each EMB. Namely the EMB in EMB configuration chain passes through the output of MUX 17 gating configuration data register 13.

Then, configuration mode selects enable signal cf_ms be set to invalid, and enable signal cf-en is set to effectively. Under the triggering of the signal rising edge of cf-clk, by configuration data register 13 write data to each EMB of mono-Bits Serial of cf-in. Further, under the triggering of the trailing edge of cf-clk signal, by the output of one Bits Serial of data in the configuration data register 13 of EMB. From there through a rising edge and a trailing edge, it is possible to make data move one in configuration data register 13.

If the data bit width of configuration data register 13 storage is n, in configuration process, need all configuration data register 13 write data, it is then: n is multiplied by EMB and configures total number of EMB in chain that the required clock cycle is also multiplied by EMB for n and configures total number of EMB in chain by the total length of cf-in write data. Same, if needing all to read the data in all configuration data register 13, needing also exist for n and being multiplied by EMB configuration chain the clock cycle of total number of EMB, being also multiplied by EMB for n by the total length of cf-out reading data and configure total number of EMB in chain.

The third situation, writes the configuration process of the mode of operation of SRAM initial value, it is possible to for:

First, configuration mode is selected enables signal cf_ms and is set to effectively, under the triggering of the signal rising edge of cf-clk, by cf-in to write 0010 in the configuration mode depositor 11 of target EMB, and in the configuration mode memorizer 11 of other EMB except target EMB, write 0000 (namely choosing bypass mode).

Then, configuration mode selects enable signal cf_ms be set to invalid, and enable signal cf-en is set to effectively. Under the triggering of the signal rising edge of cf-clk, by SRAM write data register 14 write data to target EMB of mono-Bits Serial of cf-in. Because data are the serials triggering by clock signal sends into SRAM write data register 14, therefore, for different target EMB, because it configures the position difference in chain at EMB, the delay sending into data is also different.

Such as, for EMB7 in Fig. 1, before effective data send into the SRAM write data register 14 of EMB7, SRAM write data register 14 can receive 7 invalid data, inputting data from the 8th, can be just the valid data sent into from cf-in end. Therefore, before the data that will be fed into SRAM write data register 14 store SRAM2, in addition it is also necessary to data are processed, 7 bit data sent in advance are neglected. So for any one EMB, if the n-bit data that cf-in end sends is configured in the EMB SRAM write data register 14 of m-th EMB configuring chain, it is necessary to m+n clock signal period just can complete. The data bits being ignored, identical in the EMB position configured in chain with target EMB, that is, can according to the position data m configured in position data depositor 16, length m+n process to the data that will write SRAM, it is necessary to the data length being ignored is identical with the value of position data. Neglect the data of front m position in this example.

SRAM write data register 14 is receiving the data of specified width, which width (such as n-bit) (after referring to process, neglect the data before the figure place of position data value), initiate a write operation to SRAM2, the data of n-bit are write in an address of SRAM. Preferably, initial address is from 0 address. Often initiating a write operation, address is incremented by 1, for instance illustrated a kind of situation of n=8 in Fig. 4. After SRAM write data register 14 receives 8 Bit datas, initiate a write operation to SRAM.

4th kind of situation, reads the configuration process of the mode of operation of SRAM initial value, it is possible to for:

First, configuration mode is selected enables signal cf_ms and is set to effectively, under the triggering of the signal rising edge of cf-clk, by cf-in to write 0011 in the configuration mode depositor (ms_reg) 11 of target EMB, and in the configuration mode memorizer 11 of other EMB except target EMB, write 0000 (namely choosing bypass mode).

Then, configuration mode selects enable signal cf_ms be set to invalid, and enable signal cf-en is set to effectively. Under the triggering of the signal trailing edge of cf-clk, the n-bit data read from SRAM of storage in SRAM read data register 15 is sent by mono-Bits Serial of cf-out. Sending because data are the serials triggering by clock signal, therefore, for different target EMB, because it configures the position difference in chain at EMB, the delay sending data is also different. EMB is configured to the m-th EMB of chain, n-bit data is all sent needs (n+ (total number-m of EMB configuration chain)) the individual clock cycle.

Therefore, the in-line memory EMB that the embodiment of the present invention provides configures chain structure and collocation method, by EMB is integrated with the cascade structure configuring chain, can effectively reduce the interface line quantity between Configuration Control Unit and EMB, thereby reduce the line of chip top-layer, reduce the complexity of design.

Professional should further appreciate that, the unit of each example described in conjunction with the embodiments described herein and algorithm steps, can with electronic hardware, computer software or the two be implemented in combination in, in order to clearly demonstrate the interchangeability of hardware and software, generally describe composition and the step of each example in the above description according to function. These functions perform with hardware or software mode actually, depend on application-specific and the design constraint of technical scheme. Professional and technical personnel specifically can should be used for using different methods to realize described function to each, but this realization is it is not considered that beyond the scope of this invention.

The method described in conjunction with the embodiments described herein or the step of algorithm can use the software module that hardware, processor perform, or the combination of the two is implemented. Software module can be placed in any other form of storage medium known in random access memory (RAM), internal memory, read only memory (ROM), electrically programmable ROM, electrically erasable ROM, depositor, hard disk, moveable magnetic disc, CD-ROM or technical field.

Above-described detailed description of the invention; the purpose of the present invention, technical scheme and beneficial effect have been further described; it is it should be understood that; the foregoing is only the specific embodiment of the present invention; the protection domain being not intended to limit the present invention; all within the spirit and principles in the present invention, any amendment of making, equivalent replacement, improvement etc., should be included within protection scope of the present invention.

Claims

1. in a fpga chip, in-line memory EMB configures chain structure, it is characterised in that described configuration chain includes: at least two EMB that cascade connects;

Each described EMB includes: Configuration Control Unit and SRAM SRAM;

2. configuration chain structure according to claim 1, it is characterised in that described Configuration Control Unit includes: configuration mode depositor;

3. configuration chain structure according to claim 2, it is characterised in that described Configuration Control Unit also includes: bypass register, configuration data register, SRAM write data register, SRAM read data register and position data depositor;

4. configuration chain structure according to claim 3, it is characterised in that in described position data depositor, the position data of storage is for indicating current EMB to configure the positional information in chain at described EMB.

5. configuration chain structure according to claim 4, it is characterized in that, when selecting SRAM write data register work described in signal behavior according to described configuration mode, described SRAM write data register, from the input data of the following bit position of described position data, detects the bit wide of described input data;

6. configuration chain structure according to claim 3, it is characterized in that, when selecting SRAM read data register work described in signal behavior according to described configuration mode, the data of certain bit wide are read in the detection of described SRAM read data register from a storage address of SRAM, and transfer Serial output to;

7. the collocation method of the in-line memory EMB configuration chain as described in the claims 1, it is characterised in that described method includes:

8. method according to claim 7, it is characterized in that, when described EMB configures in chain, one EMB selects signal according to the configuration mode that the configuration mode depositor in current EMB exports and enables signal cf-en, select by SRAM write data register described in current EMB, described SRAM to be configured, or read in described SRAM by described SRAM read data register data time, described method also includes: