CN103092787A

CN103092787A - PowerPC architecture based multifunctional low-power-consumption bus communication module

Info

Publication number: CN103092787A
Application number: CN2011103326042A
Authority: CN
Inventors: 温世杰; 李印国
Original assignee: No 8357 Research Institute of Third Academy of CASIC
Current assignee: No 8357 Research Institute of Third Academy of CASIC
Priority date: 2011-10-28
Filing date: 2011-10-28
Publication date: 2013-05-08

Abstract

The invention belongs to the field of data communication, and particularly relates to a multifunctional data bus communication module in the condition of low power consumption. The module adopts a mode of combining a low-end CPU (central processing unit) of a PowerPC series with an FPGA (field programmable gate array) to integrate three kinds of data buses of MIL-STD-1553B, ARINC429 and RS422 into a card. A specific implementation method of the module mainly includes: (1) connecting all the three kinds of data buses into the FPGA and then combining the data buses with an MPC8315 minimum working system through a local bus so as to form an uniform data communication platform; (2) configuring a bottom layer BSP (board support package) of MPC8315 to enable the three kinds of data buses to be adopted with an uniform data transmission protocol and guarantee consistency with an upper hardware platform; and (3) designing an internal logical circuit of the FPGA and unifying read-write operation of the three kinds of data buses into one mode so as to achieve read-write operation among the MPC8315 and the data buses. The module has the advantages that by utilizing programmability of the FPGA, the three kinds of data buses of MIL-STD-1553B, ARINC429 and RS422 are unified into one mode and then combined with the low-power-consumption CPU of the PowerPC architecture, so that multiple data bus communication functions are achieved, and power consumption of the card and a system are lowered greatly.

Description

A kind of multifunctional low power consumption bus communication module based on the PowerPC framework

Technical field

The invention belongs to the data communication field, the data communication buses such as MIL-STD-1553B, ARINC429 and RS422 are combined with the PowerPC framework CPU of low-power consumption, realize the co-ordination between the several data bus in the low-power consumption situation.

Background technology

The development of Modern Avionics synthesization technology has improved the performance of aircraft greatly, and the key of Avionics is the establishment of airborne communication network.And being based on MIL-STD-1553B, ARINC429 and RS422 etc., active service and the military aircraft overwhelming majority that developing set up multipath transmission, bus distributed avionics communication system.The special indexs such as high real-time, maneuverability and reliability that it should be noted that military secret are had higher requirement to avionics communication system.

Common bus communication solution, the one, various data buss are distributed on different integrated circuit boards, and and poor-performing, but the lower ARM series CPU of power consumption combines.This scheme has reduced design difficulty and the power consumption of veneer, but increases complexity and the power consumption of entire system, and Simultaneous Stabilization and reliability are also lower.

Another kind of scheme is, various data buss are integrated on an integrated circuit board, but x86 series CPU that power consumption large higher with performance combines.The advantage of this scheme is, board integration is high, and the system integration is convenient, and shortcoming is that power consumption is larger, the heat dissipation design of system required very high, and simultaneously, hot environment is larger to Systems balanth and reliability effect.

Summary of the invention

For this problem, we adopt the low side CPU of PowerPC framework in conjunction with the mode of FPGA, and three kinds of data buss are integrated on an integrated circuit board.This scheme is utilized the logic control of FPGA, and three kinds of data buss unifications are a kind of pattern, is articulated on the local bus of CPU, has realized the multiple bus communication in low-power consumption, low performance CPU situation.

According to the related request of model development, the CPU that we select is the MPC8315 of PowerPC series, and FPGA is the EP3C40F484 of altera corp, and three kinds of bus interface are BU-61843, HI-3582 and XR16V798IQ.The principle of the multifunction bus communication module of the present invention's design as shown in Figure 1.

Three kinds of data buss of MIL-STD-1553B, ARINC429 and RS422 all access in FPGA, and FPGA is according to current mission requirements and priority, and a kind of data of bus are wherein sent into CPU by Local bus.At this moment, the minimum work system take MPC8315 as core is equivalent to only carry out data communication for a kind of bus, greatly reduces complexity and the expense of system software, and then has reduced the power consumption of system.

The invention has the advantages that: (1) has been integrated into MIL-STD-1553B, ARINC429 and three kinds of data buss of RS422 in an integrated circuit board; (2) carry out logic control and coordination by FPGA, the uniform data communication mode has reduced the task expense of CPU; (3) can select cpu chip low in energy consumption, slightly inferior properties, thereby reduce the power consumption of whole communication module.

The explanation of accompanying drawing table

Fig. 1 is the multifunction bus communication module schematic diagram based on the PowerPC framework;

Fig. 2 is the minimum work system schematic diagram take MPC8315 as core;

Fig. 3 is FPGA write data bus process flow diagram;

Fig. 4 is FPGA read data bus process flow diagram;

Embodiment

Multifunction bus communication module as shown in Figure 1 mainly comprises following three parts: the organizational structure of hardware; The configuration of MPC8315 bottom BSP; The logic control of FPGA inside and coordination.

1) hardware configuration of multifunction bus communication module

The minimum work system of MPC8315: comprise a slice MPC8315,4 SDRAM, piece of CPLD and a slice NORFlash, as shown in Figure 2.The maximum operation frequency of MPC8315 is 400MHz, and the maximum power dissipation of kernel is 1.69W, and the maximum power dissipation that is used for articulating the Local bus of peripheral chip is 0.056W.MPC8315 greatly reduces the power consumption of system when reducing frequency of operation, and dominant frequency reduces the hydraulic performance decline that causes, and can make up by the FPGA of rear end, so just under the prerequisite that guarantees normal operation, greatly reduces the power consumption of system.

Be articulated in the FPGA on cpu local bus: at this end of cpu local bus, FPGA is connected with chip selection signal with 16 bit data bus, 25 bit address buses, read-write control signal, make MPC8315 to the read-write operation of external data bus, unification is the read-write operation to FPGA, simplify like this design effort of system software, reduced the expense of system hardware.

Three kinds of data bus: MIL-STD-1553B, ARINC429 that expand by FPGA and RS422 be all by I/O port access FPGA, and be connected with the self-built data bus of its inside.FPGA carries out decoding to the signal that transmits on Local bus address bus, converts the reading and writing signal of corresponding data bus to, completes reception and the transmission of data.

2) MPC8315 bottom BSP configuration:

On hardware structure, the read-write operation of three kinds of data buss is unified for after a kind of pattern, also need to be in bottom layer driving software (BSP), the mode of operation of uniform data bus.

The bottom BSP of the minimum work system of MPC8315 relates to the various aspects of system, and we only introduce the configuration of the data transfer mode relevant with Local bus and address space here.According to the hardware structure of multifunction bus communication module, we are with the data-transmission mode of three kinds of data buss, and the GPCM agreement is adopted in unification, and simultaneously, the address space that in config.h and two files of sisLib.c, three kinds of data buss is taken arranges.

3) logic control of FPGA inside and coordination:

The key of multifunction bus communication module is, logic control and the scheduling of FPGA to MIL-STD-1553B, ARINC429 and three kinds of data buss of RS422.

When MPC8315 carries out the data bus write operation, do not distinguish concrete data bus form, just according to pre-set address space, directly carry out the write operation order, and by FPGA, address space is carried out decoding, what convert respective bus to writes the driving signal, completes data and sends task, and its flow process as shown in Figure 3.

When MPC8315 carries out the data bus read operation, do not distinguish concrete data bus form yet, but wait for the look-at-me that FPGA provides, and according to this signal, carry out the data read command in the appropriate address space.Equally, FPGA carries out decoding to address space, and what convert respective bus to reads to drive signal, completes the data receiver task.

Look-at-me for three kinds of data buss triggerings, FPGA utilizes time slice to switch, when powering on original state, first wait for the MIL-STD-1553B look-at-me, after a period of time, wait for the ARINC429 look-at-me, after the same time, wait for the RS422 look-at-me, switch to again afterwards and wait for the MIL-STD-1553B look-at-me, so move in circles.In fragment sometime, if corresponding look-at-me is arranged, just this signal is sent into MPC8315, complete interrupt operation, if look-at-me appears in the time slice of other bus, just be in waiting status, until next circulation arrives.

FPGA flow process when MPC8315 carries out the data bus read operation as shown in Figure 4.

In sum, utilize the programmability of FPGA, MIL-STD-1553B, ARINC429 and three kinds of data buss unifications of RS422 are a kind of pattern, combine with the PowerPC framework CPU of low-power consumption again, both realize the several data bus communication function, greatly reduced again the power consumption of integrated circuit board and system.In addition, MPC8315 also is integrated with multiple other interface, has stronger expandability.

Claims

1. military multifunctional low power consumption bus communication module based on the PowerPC framework, it is characterized in that: select the low side CPU of PowerPC series to combine with FPGA, MIL-STD-1553B, ARINC429 and three kinds of data buss of RS422 is unified for a kind of pattern, be integrated in a Communication Card; This module application possesses the advantages such as low-power consumption, high-performance, high reliability when avionics system.

2. military multi-functional, low-power consumption bus communication module as described in claim 1, is characterized in that: select the low side CPU MPC8315 of PowerPC series to form minimum work system, be responsible for the data reading and writing operation of bus communication module.The maximum operation frequency of MPC8315 is 400MHz, and the maximum power dissipation of kernel is 1.69W, and the maximum power dissipation that is used for articulating the Local bus of peripheral chip is 0.056W.

3. military multi-functional, low-power consumption bus communication module as described in claim 1, it is characterized in that: MIL-STD-1553B, ARINC429 and RS422 all connect into FPGA, and be unified for after a kind of pattern by FPGA, through local bus access MPC8315.Simultaneously, in order to be consistent with hardware structure, in MPC8315 bottom BSP design, the data-transmission mode of three kinds of data buss is also unified to adopt the GPCM agreement.

4. military multi-functional, low-power consumption bus communication module as described in claim 1 is characterized in that: FPGA coordinates the data communication between MIL-STD-1553B, ARINC429 and three kinds of data buss of RS422 and CPU by inner logic control.When carrying out data write operation, FPGA carries out decoding to the address signal on local bus, and what convert respective bus to writes the driving signal; When carrying out data reading operation, FPGA utilizes time slice to coordinate look-at-me, and the address signal on local bus is carried out decoding, and what convert respective bus to reads to drive signal.